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author
Paolo Abeni
committed
Merge branch 'net-dsa-mt7530-modernize-mib-handling-fix'
Christian Marangi says: ==================== net: dsa: mt7530: modernize MIB handling + fix This small series modernize MIB handling for MT7530 and also implement .get_stats64. It was reported that kernel and Switch MIB desync in scenario where a packet is forwarded from a port to another. In such case, the forwarding is offloaded and the kernel is not aware of the transmitted packet. To handle this, read the counter directly from Switch registers. ==================== Link: https://patch.msgid.link/[email protected] Signed-off-by: Paolo Abeni <[email protected]>
2 parents 0f2be57 + 88c810f commit 4c2e0b0

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-49
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2 files changed

+239
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lines changed

‎drivers/net/dsa/mt7530.c

Lines changed: 197 additions & 49 deletions
Original file line numberDiff line numberDiff line change
@@ -32,47 +32,15 @@ static struct mt753x_pcs *pcs_to_mt753x_pcs(struct phylink_pcs *pcs)
3232

3333
/* String, offset, and register size in bytes if different from 4 bytes */
3434
static const struct mt7530_mib_desc mt7530_mib[] = {
35-
MIB_DESC(1, 0x00, "TxDrop"),
36-
MIB_DESC(1, 0x04, "TxCrcErr"),
37-
MIB_DESC(1, 0x08, "TxUnicast"),
38-
MIB_DESC(1, 0x0c, "TxMulticast"),
39-
MIB_DESC(1, 0x10, "TxBroadcast"),
40-
MIB_DESC(1, 0x14, "TxCollision"),
41-
MIB_DESC(1, 0x18, "TxSingleCollision"),
42-
MIB_DESC(1, 0x1c, "TxMultipleCollision"),
43-
MIB_DESC(1, 0x20, "TxDeferred"),
44-
MIB_DESC(1, 0x24, "TxLateCollision"),
45-
MIB_DESC(1, 0x28, "TxExcessiveCollistion"),
46-
MIB_DESC(1, 0x2c, "TxPause"),
47-
MIB_DESC(1, 0x30, "TxPktSz64"),
48-
MIB_DESC(1, 0x34, "TxPktSz65To127"),
49-
MIB_DESC(1, 0x38, "TxPktSz128To255"),
50-
MIB_DESC(1, 0x3c, "TxPktSz256To511"),
51-
MIB_DESC(1, 0x40, "TxPktSz512To1023"),
52-
MIB_DESC(1, 0x44, "Tx1024ToMax"),
53-
MIB_DESC(2, 0x48, "TxBytes"),
54-
MIB_DESC(1, 0x60, "RxDrop"),
55-
MIB_DESC(1, 0x64, "RxFiltering"),
56-
MIB_DESC(1, 0x68, "RxUnicast"),
57-
MIB_DESC(1, 0x6c, "RxMulticast"),
58-
MIB_DESC(1, 0x70, "RxBroadcast"),
59-
MIB_DESC(1, 0x74, "RxAlignErr"),
60-
MIB_DESC(1, 0x78, "RxCrcErr"),
61-
MIB_DESC(1, 0x7c, "RxUnderSizeErr"),
62-
MIB_DESC(1, 0x80, "RxFragErr"),
63-
MIB_DESC(1, 0x84, "RxOverSzErr"),
64-
MIB_DESC(1, 0x88, "RxJabberErr"),
65-
MIB_DESC(1, 0x8c, "RxPause"),
66-
MIB_DESC(1, 0x90, "RxPktSz64"),
67-
MIB_DESC(1, 0x94, "RxPktSz65To127"),
68-
MIB_DESC(1, 0x98, "RxPktSz128To255"),
69-
MIB_DESC(1, 0x9c, "RxPktSz256To511"),
70-
MIB_DESC(1, 0xa0, "RxPktSz512To1023"),
71-
MIB_DESC(1, 0xa4, "RxPktSz1024ToMax"),
72-
MIB_DESC(2, 0xa8, "RxBytes"),
73-
MIB_DESC(1, 0xb0, "RxCtrlDrop"),
74-
MIB_DESC(1, 0xb4, "RxIngressDrop"),
75-
MIB_DESC(1, 0xb8, "RxArlDrop"),
35+
MIB_DESC(1, MT7530_PORT_MIB_TX_DROP, "TxDrop"),
36+
MIB_DESC(1, MT7530_PORT_MIB_TX_CRC_ERR, "TxCrcErr"),
37+
MIB_DESC(1, MT7530_PORT_MIB_TX_COLLISION, "TxCollision"),
38+
MIB_DESC(1, MT7530_PORT_MIB_RX_DROP, "RxDrop"),
39+
MIB_DESC(1, MT7530_PORT_MIB_RX_FILTERING, "RxFiltering"),
40+
MIB_DESC(1, MT7530_PORT_MIB_RX_CRC_ERR, "RxCrcErr"),
41+
MIB_DESC(1, MT7530_PORT_MIB_RX_CTRL_DROP, "RxCtrlDrop"),
42+
MIB_DESC(1, MT7530_PORT_MIB_RX_INGRESS_DROP, "RxIngressDrop"),
43+
MIB_DESC(1, MT7530_PORT_MIB_RX_ARL_DROP, "RxArlDrop"),
7644
};
7745

7846
static void
@@ -789,24 +757,34 @@ mt7530_get_strings(struct dsa_switch *ds, int port, u32 stringset,
789757
ethtool_puts(&data, mt7530_mib[i].name);
790758
}
791759

760+
static void
761+
mt7530_read_port_stats(struct mt7530_priv *priv, int port,
762+
u32 offset, u8 size, uint64_t *data)
763+
{
764+
u32 val, reg = MT7530_PORT_MIB_COUNTER(port) + offset;
765+
766+
val = mt7530_read(priv, reg);
767+
*data = val;
768+
769+
if (size == 2) {
770+
val = mt7530_read(priv, reg + 4);
771+
*data |= (u64)val << 32;
772+
}
773+
}
774+
792775
static void
793776
mt7530_get_ethtool_stats(struct dsa_switch *ds, int port,
794777
uint64_t *data)
795778
{
796779
struct mt7530_priv *priv = ds->priv;
797780
const struct mt7530_mib_desc *mib;
798-
u32 reg, i;
799-
u64 hi;
781+
int i;
800782

801783
for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++) {
802784
mib = &mt7530_mib[i];
803-
reg = MT7530_PORT_MIB_COUNTER(port) + mib->offset;
804785

805-
data[i] = mt7530_read(priv, reg);
806-
if (mib->size == 2) {
807-
hi = mt7530_read(priv, reg + 4);
808-
data[i] |= hi << 32;
809-
}
786+
mt7530_read_port_stats(priv, port, mib->offset, mib->size,
787+
data + i);
810788
}
811789
}
812790

@@ -819,6 +797,172 @@ mt7530_get_sset_count(struct dsa_switch *ds, int port, int sset)
819797
return ARRAY_SIZE(mt7530_mib);
820798
}
821799

800+
static void mt7530_get_eth_mac_stats(struct dsa_switch *ds, int port,
801+
struct ethtool_eth_mac_stats *mac_stats)
802+
{
803+
struct mt7530_priv *priv = ds->priv;
804+
805+
/* MIB counter doesn't provide a FramesTransmittedOK but instead
806+
* provide stats for Unicast, Broadcast and Multicast frames separately.
807+
* To simulate a global frame counter, read Unicast and addition Multicast
808+
* and Broadcast later
809+
*/
810+
mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_UNICAST, 1,
811+
&mac_stats->FramesTransmittedOK);
812+
813+
mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_SINGLE_COLLISION, 1,
814+
&mac_stats->SingleCollisionFrames);
815+
816+
mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_MULTIPLE_COLLISION, 1,
817+
&mac_stats->MultipleCollisionFrames);
818+
819+
mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_UNICAST, 1,
820+
&mac_stats->FramesReceivedOK);
821+
822+
mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_BYTES, 2,
823+
&mac_stats->OctetsTransmittedOK);
824+
825+
mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_ALIGN_ERR, 1,
826+
&mac_stats->AlignmentErrors);
827+
828+
mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_DEFERRED, 1,
829+
&mac_stats->FramesWithDeferredXmissions);
830+
831+
mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_LATE_COLLISION, 1,
832+
&mac_stats->LateCollisions);
833+
834+
mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_EXCESSIVE_COLLISION, 1,
835+
&mac_stats->FramesAbortedDueToXSColls);
836+
837+
mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_BYTES, 2,
838+
&mac_stats->OctetsReceivedOK);
839+
840+
mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_MULTICAST, 1,
841+
&mac_stats->MulticastFramesXmittedOK);
842+
mac_stats->FramesTransmittedOK += mac_stats->MulticastFramesXmittedOK;
843+
mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_BROADCAST, 1,
844+
&mac_stats->BroadcastFramesXmittedOK);
845+
mac_stats->FramesTransmittedOK += mac_stats->BroadcastFramesXmittedOK;
846+
847+
mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_MULTICAST, 1,
848+
&mac_stats->MulticastFramesReceivedOK);
849+
mac_stats->FramesReceivedOK += mac_stats->MulticastFramesReceivedOK;
850+
mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_BROADCAST, 1,
851+
&mac_stats->BroadcastFramesReceivedOK);
852+
mac_stats->FramesReceivedOK += mac_stats->BroadcastFramesReceivedOK;
853+
}
854+
855+
static const struct ethtool_rmon_hist_range mt7530_rmon_ranges[] = {
856+
{ 0, 64 },
857+
{ 65, 127 },
858+
{ 128, 255 },
859+
{ 256, 511 },
860+
{ 512, 1023 },
861+
{ 1024, MT7530_MAX_MTU },
862+
{}
863+
};
864+
865+
static void mt7530_get_rmon_stats(struct dsa_switch *ds, int port,
866+
struct ethtool_rmon_stats *rmon_stats,
867+
const struct ethtool_rmon_hist_range **ranges)
868+
{
869+
struct mt7530_priv *priv = ds->priv;
870+
871+
mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_UNDER_SIZE_ERR, 1,
872+
&rmon_stats->undersize_pkts);
873+
mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_OVER_SZ_ERR, 1,
874+
&rmon_stats->oversize_pkts);
875+
mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_FRAG_ERR, 1,
876+
&rmon_stats->fragments);
877+
mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_JABBER_ERR, 1,
878+
&rmon_stats->jabbers);
879+
880+
mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_PKT_SZ_64, 1,
881+
&rmon_stats->hist[0]);
882+
mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_PKT_SZ_65_TO_127, 1,
883+
&rmon_stats->hist[1]);
884+
mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_PKT_SZ_128_TO_255, 1,
885+
&rmon_stats->hist[2]);
886+
mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_PKT_SZ_256_TO_511, 1,
887+
&rmon_stats->hist[3]);
888+
mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_PKT_SZ_512_TO_1023, 1,
889+
&rmon_stats->hist[4]);
890+
mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_PKT_SZ_1024_TO_MAX, 1,
891+
&rmon_stats->hist[5]);
892+
893+
mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_PKT_SZ_64, 1,
894+
&rmon_stats->hist_tx[0]);
895+
mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_PKT_SZ_65_TO_127, 1,
896+
&rmon_stats->hist_tx[1]);
897+
mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_PKT_SZ_128_TO_255, 1,
898+
&rmon_stats->hist_tx[2]);
899+
mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_PKT_SZ_256_TO_511, 1,
900+
&rmon_stats->hist_tx[3]);
901+
mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_PKT_SZ_512_TO_1023, 1,
902+
&rmon_stats->hist_tx[4]);
903+
mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_PKT_SZ_1024_TO_MAX, 1,
904+
&rmon_stats->hist_tx[5]);
905+
906+
*ranges = mt7530_rmon_ranges;
907+
}
908+
909+
static void mt7530_get_stats64(struct dsa_switch *ds, int port,
910+
struct rtnl_link_stats64 *storage)
911+
{
912+
struct mt7530_priv *priv = ds->priv;
913+
uint64_t data;
914+
915+
/* MIB counter doesn't provide a FramesTransmittedOK but instead
916+
* provide stats for Unicast, Broadcast and Multicast frames separately.
917+
* To simulate a global frame counter, read Unicast and addition Multicast
918+
* and Broadcast later
919+
*/
920+
mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_UNICAST, 1,
921+
&storage->rx_packets);
922+
mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_MULTICAST, 1,
923+
&storage->multicast);
924+
storage->rx_packets += storage->multicast;
925+
mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_BROADCAST, 1,
926+
&data);
927+
storage->rx_packets += data;
928+
929+
mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_UNICAST, 1,
930+
&storage->tx_packets);
931+
mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_MULTICAST, 1,
932+
&data);
933+
storage->tx_packets += data;
934+
mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_BROADCAST, 1,
935+
&data);
936+
storage->tx_packets += data;
937+
938+
mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_BYTES, 2,
939+
&storage->rx_bytes);
940+
941+
mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_BYTES, 2,
942+
&storage->tx_bytes);
943+
944+
mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_DROP, 1,
945+
&storage->rx_dropped);
946+
947+
mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_DROP, 1,
948+
&storage->tx_dropped);
949+
950+
mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_CRC_ERR, 1,
951+
&storage->rx_crc_errors);
952+
}
953+
954+
static void mt7530_get_eth_ctrl_stats(struct dsa_switch *ds, int port,
955+
struct ethtool_eth_ctrl_stats *ctrl_stats)
956+
{
957+
struct mt7530_priv *priv = ds->priv;
958+
959+
mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_PAUSE, 1,
960+
&ctrl_stats->MACControlFramesTransmitted);
961+
962+
mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_PAUSE, 1,
963+
&ctrl_stats->MACControlFramesReceived);
964+
}
965+
822966
static int
823967
mt7530_set_ageing_time(struct dsa_switch *ds, unsigned int msecs)
824968
{
@@ -3105,6 +3249,10 @@ const struct dsa_switch_ops mt7530_switch_ops = {
31053249
.get_strings = mt7530_get_strings,
31063250
.get_ethtool_stats = mt7530_get_ethtool_stats,
31073251
.get_sset_count = mt7530_get_sset_count,
3252+
.get_eth_mac_stats = mt7530_get_eth_mac_stats,
3253+
.get_rmon_stats = mt7530_get_rmon_stats,
3254+
.get_eth_ctrl_stats = mt7530_get_eth_ctrl_stats,
3255+
.get_stats64 = mt7530_get_stats64,
31083256
.set_ageing_time = mt7530_set_ageing_time,
31093257
.port_enable = mt7530_port_enable,
31103258
.port_disable = mt7530_port_disable,

‎drivers/net/dsa/mt7530.h

Lines changed: 42 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -423,6 +423,48 @@ enum mt7530_vlan_port_acc_frm {
423423

424424
/* Register for MIB */
425425
#define MT7530_PORT_MIB_COUNTER(x) (0x4000 + (x) * 0x100)
426+
/* Each define is an offset of MT7530_PORT_MIB_COUNTER */
427+
#define MT7530_PORT_MIB_TX_DROP 0x00
428+
#define MT7530_PORT_MIB_TX_CRC_ERR 0x04
429+
#define MT7530_PORT_MIB_TX_UNICAST 0x08
430+
#define MT7530_PORT_MIB_TX_MULTICAST 0x0c
431+
#define MT7530_PORT_MIB_TX_BROADCAST 0x10
432+
#define MT7530_PORT_MIB_TX_COLLISION 0x14
433+
#define MT7530_PORT_MIB_TX_SINGLE_COLLISION 0x18
434+
#define MT7530_PORT_MIB_TX_MULTIPLE_COLLISION 0x1c
435+
#define MT7530_PORT_MIB_TX_DEFERRED 0x20
436+
#define MT7530_PORT_MIB_TX_LATE_COLLISION 0x24
437+
#define MT7530_PORT_MIB_TX_EXCESSIVE_COLLISION 0x28
438+
#define MT7530_PORT_MIB_TX_PAUSE 0x2c
439+
#define MT7530_PORT_MIB_TX_PKT_SZ_64 0x30
440+
#define MT7530_PORT_MIB_TX_PKT_SZ_65_TO_127 0x34
441+
#define MT7530_PORT_MIB_TX_PKT_SZ_128_TO_255 0x38
442+
#define MT7530_PORT_MIB_TX_PKT_SZ_256_TO_511 0x3c
443+
#define MT7530_PORT_MIB_TX_PKT_SZ_512_TO_1023 0x40
444+
#define MT7530_PORT_MIB_TX_PKT_SZ_1024_TO_MAX 0x44
445+
#define MT7530_PORT_MIB_TX_BYTES 0x48 /* 64 bytes */
446+
#define MT7530_PORT_MIB_RX_DROP 0x60
447+
#define MT7530_PORT_MIB_RX_FILTERING 0x64
448+
#define MT7530_PORT_MIB_RX_UNICAST 0x68
449+
#define MT7530_PORT_MIB_RX_MULTICAST 0x6c
450+
#define MT7530_PORT_MIB_RX_BROADCAST 0x70
451+
#define MT7530_PORT_MIB_RX_ALIGN_ERR 0x74
452+
#define MT7530_PORT_MIB_RX_CRC_ERR 0x78
453+
#define MT7530_PORT_MIB_RX_UNDER_SIZE_ERR 0x7c
454+
#define MT7530_PORT_MIB_RX_FRAG_ERR 0x80
455+
#define MT7530_PORT_MIB_RX_OVER_SZ_ERR 0x84
456+
#define MT7530_PORT_MIB_RX_JABBER_ERR 0x88
457+
#define MT7530_PORT_MIB_RX_PAUSE 0x8c
458+
#define MT7530_PORT_MIB_RX_PKT_SZ_64 0x90
459+
#define MT7530_PORT_MIB_RX_PKT_SZ_65_TO_127 0x94
460+
#define MT7530_PORT_MIB_RX_PKT_SZ_128_TO_255 0x98
461+
#define MT7530_PORT_MIB_RX_PKT_SZ_256_TO_511 0x9c
462+
#define MT7530_PORT_MIB_RX_PKT_SZ_512_TO_1023 0xa0
463+
#define MT7530_PORT_MIB_RX_PKT_SZ_1024_TO_MAX 0xa4
464+
#define MT7530_PORT_MIB_RX_BYTES 0xa8 /* 64 bytes */
465+
#define MT7530_PORT_MIB_RX_CTRL_DROP 0xb0
466+
#define MT7530_PORT_MIB_RX_INGRESS_DROP 0xb4
467+
#define MT7530_PORT_MIB_RX_ARL_DROP 0xb8
426468
#define MT7530_MIB_CCR 0x4fe0
427469
#define CCR_MIB_ENABLE BIT(31)
428470
#define CCR_RX_OCT_CNT_GOOD BIT(7)

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