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Move specific features settings from EP shared code
(pcie-designware-ep.c) to the driver (pcie-designware-plat.c).
Previous implementation disables the EP link notification
by default for all SoCs that uses EP DesignWare IP, which affects
directly the dra7xx and artpec6 SoCs.
Signed-off-by: Gustavo Pimentel <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Acked-by: Kishon Vijay Abraham I <[email protected]>
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