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Jia ZhangIngo Molnar
Jia Zhang
authored and
Ingo Molnar
committed
x86/cpu: Rename cpu_data.x86_mask to cpu_data.x86_stepping
x86_mask is a confusing name which is hard to associate with the processor's stepping. Additionally, correct an indent issue in lib/cpu.c. Signed-off-by: Jia Zhang <[email protected]> [ Updated it to more recent kernels. ] Cc: Linus Torvalds <[email protected]> Cc: Peter Zijlstra <[email protected]> Cc: Thomas Gleixner <[email protected]> Cc: [email protected] Cc: [email protected] Link: http://lkml.kernel.org/r/[email protected] Signed-off-by: Ingo Molnar <[email protected]>
1 parent 961888b commit b399151

35 files changed

+73
-73
lines changed

‎arch/x86/events/intel/core.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3559,7 +3559,7 @@ static int intel_snb_pebs_broken(int cpu)
35593559
break;
35603560

35613561
case INTEL_FAM6_SANDYBRIDGE_X:
3562-
switch (cpu_data(cpu).x86_mask) {
3562+
switch (cpu_data(cpu).x86_stepping) {
35633563
case 6: rev = 0x618; break;
35643564
case 7: rev = 0x70c; break;
35653565
}

‎arch/x86/events/intel/lbr.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1186,7 +1186,7 @@ void __init intel_pmu_lbr_init_atom(void)
11861186
* on PMU interrupt
11871187
*/
11881188
if (boot_cpu_data.x86_model == 28
1189-
&& boot_cpu_data.x86_mask < 10) {
1189+
&& boot_cpu_data.x86_stepping < 10) {
11901190
pr_cont("LBR disabled due to erratum");
11911191
return;
11921192
}

‎arch/x86/events/intel/p6.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -234,7 +234,7 @@ static __initconst const struct x86_pmu p6_pmu = {
234234

235235
static __init void p6_pmu_rdpmc_quirk(void)
236236
{
237-
if (boot_cpu_data.x86_mask < 9) {
237+
if (boot_cpu_data.x86_stepping < 9) {
238238
/*
239239
* PPro erratum 26; fixed in stepping 9 and above.
240240
*/

‎arch/x86/include/asm/acpi.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -94,7 +94,7 @@ static inline unsigned int acpi_processor_cstate_check(unsigned int max_cstate)
9494
if (boot_cpu_data.x86 == 0x0F &&
9595
boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
9696
boot_cpu_data.x86_model <= 0x05 &&
97-
boot_cpu_data.x86_mask < 0x0A)
97+
boot_cpu_data.x86_stepping < 0x0A)
9898
return 1;
9999
else if (boot_cpu_has(X86_BUG_AMD_APIC_C1E))
100100
return 1;

‎arch/x86/include/asm/processor.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -91,7 +91,7 @@ struct cpuinfo_x86 {
9191
__u8 x86; /* CPU family */
9292
__u8 x86_vendor; /* CPU vendor */
9393
__u8 x86_model;
94-
__u8 x86_mask;
94+
__u8 x86_stepping;
9595
#ifdef CONFIG_X86_64
9696
/* Number of 4K pages in DTLB/ITLB combined(in pages): */
9797
int x86_tlbsize;

‎arch/x86/kernel/amd_nb.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -235,7 +235,7 @@ int amd_cache_northbridges(void)
235235
if (boot_cpu_data.x86 == 0x10 &&
236236
boot_cpu_data.x86_model >= 0x8 &&
237237
(boot_cpu_data.x86_model > 0x9 ||
238-
boot_cpu_data.x86_mask >= 0x1))
238+
boot_cpu_data.x86_stepping >= 0x1))
239239
amd_northbridges.flags |= AMD_NB_L3_INDEX_DISABLE;
240240

241241
if (boot_cpu_data.x86 == 0x15)

‎arch/x86/kernel/apic/apic.c

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -546,7 +546,7 @@ static DEFINE_PER_CPU(struct clock_event_device, lapic_events);
546546

547547
static u32 hsx_deadline_rev(void)
548548
{
549-
switch (boot_cpu_data.x86_mask) {
549+
switch (boot_cpu_data.x86_stepping) {
550550
case 0x02: return 0x3a; /* EP */
551551
case 0x04: return 0x0f; /* EX */
552552
}
@@ -556,7 +556,7 @@ static u32 hsx_deadline_rev(void)
556556

557557
static u32 bdx_deadline_rev(void)
558558
{
559-
switch (boot_cpu_data.x86_mask) {
559+
switch (boot_cpu_data.x86_stepping) {
560560
case 0x02: return 0x00000011;
561561
case 0x03: return 0x0700000e;
562562
case 0x04: return 0x0f00000c;
@@ -568,7 +568,7 @@ static u32 bdx_deadline_rev(void)
568568

569569
static u32 skx_deadline_rev(void)
570570
{
571-
switch (boot_cpu_data.x86_mask) {
571+
switch (boot_cpu_data.x86_stepping) {
572572
case 0x03: return 0x01000136;
573573
case 0x04: return 0x02000014;
574574
}

‎arch/x86/kernel/asm-offsets_32.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -18,7 +18,7 @@ void foo(void)
1818
OFFSET(CPUINFO_x86, cpuinfo_x86, x86);
1919
OFFSET(CPUINFO_x86_vendor, cpuinfo_x86, x86_vendor);
2020
OFFSET(CPUINFO_x86_model, cpuinfo_x86, x86_model);
21-
OFFSET(CPUINFO_x86_mask, cpuinfo_x86, x86_mask);
21+
OFFSET(CPUINFO_x86_stepping, cpuinfo_x86, x86_stepping);
2222
OFFSET(CPUINFO_cpuid_level, cpuinfo_x86, cpuid_level);
2323
OFFSET(CPUINFO_x86_capability, cpuinfo_x86, x86_capability);
2424
OFFSET(CPUINFO_x86_vendor_id, cpuinfo_x86, x86_vendor_id);

‎arch/x86/kernel/cpu/amd.c

Lines changed: 14 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -119,7 +119,7 @@ static void init_amd_k6(struct cpuinfo_x86 *c)
119119
return;
120120
}
121121

122-
if (c->x86_model == 6 && c->x86_mask == 1) {
122+
if (c->x86_model == 6 && c->x86_stepping == 1) {
123123
const int K6_BUG_LOOP = 1000000;
124124
int n;
125125
void (*f_vide)(void);
@@ -149,7 +149,7 @@ static void init_amd_k6(struct cpuinfo_x86 *c)
149149

150150
/* K6 with old style WHCR */
151151
if (c->x86_model < 8 ||
152-
(c->x86_model == 8 && c->x86_mask < 8)) {
152+
(c->x86_model == 8 && c->x86_stepping < 8)) {
153153
/* We can only write allocate on the low 508Mb */
154154
if (mbytes > 508)
155155
mbytes = 508;
@@ -168,7 +168,7 @@ static void init_amd_k6(struct cpuinfo_x86 *c)
168168
return;
169169
}
170170

171-
if ((c->x86_model == 8 && c->x86_mask > 7) ||
171+
if ((c->x86_model == 8 && c->x86_stepping > 7) ||
172172
c->x86_model == 9 || c->x86_model == 13) {
173173
/* The more serious chips .. */
174174

@@ -221,7 +221,7 @@ static void init_amd_k7(struct cpuinfo_x86 *c)
221221
* are more robust with CLK_CTL set to 200xxxxx instead of 600xxxxx
222222
* As per AMD technical note 27212 0.2
223223
*/
224-
if ((c->x86_model == 8 && c->x86_mask >= 1) || (c->x86_model > 8)) {
224+
if ((c->x86_model == 8 && c->x86_stepping >= 1) || (c->x86_model > 8)) {
225225
rdmsr(MSR_K7_CLK_CTL, l, h);
226226
if ((l & 0xfff00000) != 0x20000000) {
227227
pr_info("CPU: CLK_CTL MSR was %x. Reprogramming to %x\n",
@@ -241,12 +241,12 @@ static void init_amd_k7(struct cpuinfo_x86 *c)
241241
* but they are not certified as MP capable.
242242
*/
243243
/* Athlon 660/661 is valid. */
244-
if ((c->x86_model == 6) && ((c->x86_mask == 0) ||
245-
(c->x86_mask == 1)))
244+
if ((c->x86_model == 6) && ((c->x86_stepping == 0) ||
245+
(c->x86_stepping == 1)))
246246
return;
247247

248248
/* Duron 670 is valid */
249-
if ((c->x86_model == 7) && (c->x86_mask == 0))
249+
if ((c->x86_model == 7) && (c->x86_stepping == 0))
250250
return;
251251

252252
/*
@@ -256,8 +256,8 @@ static void init_amd_k7(struct cpuinfo_x86 *c)
256256
* See http://www.heise.de/newsticker/data/jow-18.10.01-000 for
257257
* more.
258258
*/
259-
if (((c->x86_model == 6) && (c->x86_mask >= 2)) ||
260-
((c->x86_model == 7) && (c->x86_mask >= 1)) ||
259+
if (((c->x86_model == 6) && (c->x86_stepping >= 2)) ||
260+
((c->x86_model == 7) && (c->x86_stepping >= 1)) ||
261261
(c->x86_model > 7))
262262
if (cpu_has(c, X86_FEATURE_MP))
263263
return;
@@ -583,7 +583,7 @@ static void early_init_amd(struct cpuinfo_x86 *c)
583583
/* Set MTRR capability flag if appropriate */
584584
if (c->x86 == 5)
585585
if (c->x86_model == 13 || c->x86_model == 9 ||
586-
(c->x86_model == 8 && c->x86_mask >= 8))
586+
(c->x86_model == 8 && c->x86_stepping >= 8))
587587
set_cpu_cap(c, X86_FEATURE_K6_MTRR);
588588
#endif
589589
#if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_PCI)
@@ -769,7 +769,7 @@ static void init_amd_zn(struct cpuinfo_x86 *c)
769769
* Fix erratum 1076: CPB feature bit not being set in CPUID. It affects
770770
* all up to and including B1.
771771
*/
772-
if (c->x86_model <= 1 && c->x86_mask <= 1)
772+
if (c->x86_model <= 1 && c->x86_stepping <= 1)
773773
set_cpu_cap(c, X86_FEATURE_CPB);
774774
}
775775

@@ -880,11 +880,11 @@ static unsigned int amd_size_cache(struct cpuinfo_x86 *c, unsigned int size)
880880
/* AMD errata T13 (order #21922) */
881881
if ((c->x86 == 6)) {
882882
/* Duron Rev A0 */
883-
if (c->x86_model == 3 && c->x86_mask == 0)
883+
if (c->x86_model == 3 && c->x86_stepping == 0)
884884
size = 64;
885885
/* Tbird rev A1/A2 */
886886
if (c->x86_model == 4 &&
887-
(c->x86_mask == 0 || c->x86_mask == 1))
887+
(c->x86_stepping == 0 || c->x86_stepping == 1))
888888
size = 256;
889889
}
890890
return size;
@@ -1021,7 +1021,7 @@ static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum)
10211021
}
10221022

10231023
/* OSVW unavailable or ID unknown, match family-model-stepping range */
1024-
ms = (cpu->x86_model << 4) | cpu->x86_mask;
1024+
ms = (cpu->x86_model << 4) | cpu->x86_stepping;
10251025
while ((range = *erratum++))
10261026
if ((cpu->x86 == AMD_MODEL_RANGE_FAMILY(range)) &&
10271027
(ms >= AMD_MODEL_RANGE_START(range)) &&

‎arch/x86/kernel/cpu/centaur.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -136,7 +136,7 @@ static void init_centaur(struct cpuinfo_x86 *c)
136136
clear_cpu_cap(c, X86_FEATURE_TSC);
137137
break;
138138
case 8:
139-
switch (c->x86_mask) {
139+
switch (c->x86_stepping) {
140140
default:
141141
name = "2";
142142
break;
@@ -211,7 +211,7 @@ centaur_size_cache(struct cpuinfo_x86 *c, unsigned int size)
211211
* - Note, it seems this may only be in engineering samples.
212212
*/
213213
if ((c->x86 == 6) && (c->x86_model == 9) &&
214-
(c->x86_mask == 1) && (size == 65))
214+
(c->x86_stepping == 1) && (size == 65))
215215
size -= 1;
216216
return size;
217217
}

‎arch/x86/kernel/cpu/common.c

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -731,7 +731,7 @@ void cpu_detect(struct cpuinfo_x86 *c)
731731
cpuid(0x00000001, &tfms, &misc, &junk, &cap0);
732732
c->x86 = x86_family(tfms);
733733
c->x86_model = x86_model(tfms);
734-
c->x86_mask = x86_stepping(tfms);
734+
c->x86_stepping = x86_stepping(tfms);
735735

736736
if (cap0 & (1<<19)) {
737737
c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
@@ -1186,7 +1186,7 @@ static void identify_cpu(struct cpuinfo_x86 *c)
11861186
c->loops_per_jiffy = loops_per_jiffy;
11871187
c->x86_cache_size = -1;
11881188
c->x86_vendor = X86_VENDOR_UNKNOWN;
1189-
c->x86_model = c->x86_mask = 0; /* So far unknown... */
1189+
c->x86_model = c->x86_stepping = 0; /* So far unknown... */
11901190
c->x86_vendor_id[0] = '\0'; /* Unset */
11911191
c->x86_model_id[0] = '\0'; /* Unset */
11921192
c->x86_max_cores = 1;
@@ -1378,8 +1378,8 @@ void print_cpu_info(struct cpuinfo_x86 *c)
13781378

13791379
pr_cont(" (family: 0x%x, model: 0x%x", c->x86, c->x86_model);
13801380

1381-
if (c->x86_mask || c->cpuid_level >= 0)
1382-
pr_cont(", stepping: 0x%x)\n", c->x86_mask);
1381+
if (c->x86_stepping || c->cpuid_level >= 0)
1382+
pr_cont(", stepping: 0x%x)\n", c->x86_stepping);
13831383
else
13841384
pr_cont(")\n");
13851385
}

‎arch/x86/kernel/cpu/cyrix.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -215,7 +215,7 @@ static void init_cyrix(struct cpuinfo_x86 *c)
215215

216216
/* common case step number/rev -- exceptions handled below */
217217
c->x86_model = (dir1 >> 4) + 1;
218-
c->x86_mask = dir1 & 0xf;
218+
c->x86_stepping = dir1 & 0xf;
219219

220220
/* Now cook; the original recipe is by Channing Corn, from Cyrix.
221221
* We do the same thing for each generation: we work out

‎arch/x86/kernel/cpu/intel.c

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -146,7 +146,7 @@ static bool bad_spectre_microcode(struct cpuinfo_x86 *c)
146146

147147
for (i = 0; i < ARRAY_SIZE(spectre_bad_microcodes); i++) {
148148
if (c->x86_model == spectre_bad_microcodes[i].model &&
149-
c->x86_mask == spectre_bad_microcodes[i].stepping)
149+
c->x86_stepping == spectre_bad_microcodes[i].stepping)
150150
return (c->microcode <= spectre_bad_microcodes[i].microcode);
151151
}
152152
return false;
@@ -193,7 +193,7 @@ static void early_init_intel(struct cpuinfo_x86 *c)
193193
* need the microcode to have already been loaded... so if it is
194194
* not, recommend a BIOS update and disable large pages.
195195
*/
196-
if (c->x86 == 6 && c->x86_model == 0x1c && c->x86_mask <= 2 &&
196+
if (c->x86 == 6 && c->x86_model == 0x1c && c->x86_stepping <= 2 &&
197197
c->microcode < 0x20e) {
198198
pr_warn("Atom PSE erratum detected, BIOS microcode update recommended\n");
199199
clear_cpu_cap(c, X86_FEATURE_PSE);
@@ -209,7 +209,7 @@ static void early_init_intel(struct cpuinfo_x86 *c)
209209

210210
/* CPUID workaround for 0F33/0F34 CPU */
211211
if (c->x86 == 0xF && c->x86_model == 0x3
212-
&& (c->x86_mask == 0x3 || c->x86_mask == 0x4))
212+
&& (c->x86_stepping == 0x3 || c->x86_stepping == 0x4))
213213
c->x86_phys_bits = 36;
214214

215215
/*
@@ -307,7 +307,7 @@ int ppro_with_ram_bug(void)
307307
if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
308308
boot_cpu_data.x86 == 6 &&
309309
boot_cpu_data.x86_model == 1 &&
310-
boot_cpu_data.x86_mask < 8) {
310+
boot_cpu_data.x86_stepping < 8) {
311311
pr_info("Pentium Pro with Errata#50 detected. Taking evasive action.\n");
312312
return 1;
313313
}
@@ -324,7 +324,7 @@ static void intel_smp_check(struct cpuinfo_x86 *c)
324324
* Mask B, Pentium, but not Pentium MMX
325325
*/
326326
if (c->x86 == 5 &&
327-
c->x86_mask >= 1 && c->x86_mask <= 4 &&
327+
c->x86_stepping >= 1 && c->x86_stepping <= 4 &&
328328
c->x86_model <= 3) {
329329
/*
330330
* Remember we have B step Pentia with bugs
@@ -367,7 +367,7 @@ static void intel_workarounds(struct cpuinfo_x86 *c)
367367
* SEP CPUID bug: Pentium Pro reports SEP but doesn't have it until
368368
* model 3 mask 3
369369
*/
370-
if ((c->x86<<8 | c->x86_model<<4 | c->x86_mask) < 0x633)
370+
if ((c->x86<<8 | c->x86_model<<4 | c->x86_stepping) < 0x633)
371371
clear_cpu_cap(c, X86_FEATURE_SEP);
372372

373373
/*
@@ -385,7 +385,7 @@ static void intel_workarounds(struct cpuinfo_x86 *c)
385385
* P4 Xeon erratum 037 workaround.
386386
* Hardware prefetcher may cause stale data to be loaded into the cache.
387387
*/
388-
if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_mask == 1)) {
388+
if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_stepping == 1)) {
389389
if (msr_set_bit(MSR_IA32_MISC_ENABLE,
390390
MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT) > 0) {
391391
pr_info("CPU: C0 stepping P4 Xeon detected.\n");
@@ -400,7 +400,7 @@ static void intel_workarounds(struct cpuinfo_x86 *c)
400400
* Specification Update").
401401
*/
402402
if (boot_cpu_has(X86_FEATURE_APIC) && (c->x86<<8 | c->x86_model<<4) == 0x520 &&
403-
(c->x86_mask < 0x6 || c->x86_mask == 0xb))
403+
(c->x86_stepping < 0x6 || c->x86_stepping == 0xb))
404404
set_cpu_bug(c, X86_BUG_11AP);
405405

406406

@@ -647,7 +647,7 @@ static void init_intel(struct cpuinfo_x86 *c)
647647
case 6:
648648
if (l2 == 128)
649649
p = "Celeron (Mendocino)";
650-
else if (c->x86_mask == 0 || c->x86_mask == 5)
650+
else if (c->x86_stepping == 0 || c->x86_stepping == 5)
651651
p = "Celeron-A";
652652
break;
653653

‎arch/x86/kernel/cpu/intel_rdt.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -771,7 +771,7 @@ static __init void rdt_quirks(void)
771771
cache_alloc_hsw_probe();
772772
break;
773773
case INTEL_FAM6_SKYLAKE_X:
774-
if (boot_cpu_data.x86_mask <= 4)
774+
if (boot_cpu_data.x86_stepping <= 4)
775775
set_rdt_options("!cmt,!mbmtotal,!mbmlocal,!l3cat");
776776
}
777777
}

‎arch/x86/kernel/cpu/microcode/intel.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -921,7 +921,7 @@ static bool is_blacklisted(unsigned int cpu)
921921
*/
922922
if (c->x86 == 6 &&
923923
c->x86_model == INTEL_FAM6_BROADWELL_X &&
924-
c->x86_mask == 0x01 &&
924+
c->x86_stepping == 0x01 &&
925925
llc_size_per_core > 2621440 &&
926926
c->microcode < 0x0b000021) {
927927
pr_err_once("Erratum BDF90: late loading with revision < 0x0b000021 (0x%x) disabled.\n", c->microcode);
@@ -944,7 +944,7 @@ static enum ucode_state request_microcode_fw(int cpu, struct device *device,
944944
return UCODE_NFOUND;
945945

946946
sprintf(name, "intel-ucode/%02x-%02x-%02x",
947-
c->x86, c->x86_model, c->x86_mask);
947+
c->x86, c->x86_model, c->x86_stepping);
948948

949949
if (request_firmware_direct(&firmware, name, device)) {
950950
pr_debug("data file %s load failed\n", name);

‎arch/x86/kernel/cpu/mtrr/generic.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -859,7 +859,7 @@ int generic_validate_add_page(unsigned long base, unsigned long size,
859859
*/
860860
if (is_cpu(INTEL) && boot_cpu_data.x86 == 6 &&
861861
boot_cpu_data.x86_model == 1 &&
862-
boot_cpu_data.x86_mask <= 7) {
862+
boot_cpu_data.x86_stepping <= 7) {
863863
if (base & ((1 << (22 - PAGE_SHIFT)) - 1)) {
864864
pr_warn("mtrr: base(0x%lx000) is not 4 MiB aligned\n", base);
865865
return -EINVAL;

‎arch/x86/kernel/cpu/mtrr/main.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -711,8 +711,8 @@ void __init mtrr_bp_init(void)
711711
if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
712712
boot_cpu_data.x86 == 0xF &&
713713
boot_cpu_data.x86_model == 0x3 &&
714-
(boot_cpu_data.x86_mask == 0x3 ||
715-
boot_cpu_data.x86_mask == 0x4))
714+
(boot_cpu_data.x86_stepping == 0x3 ||
715+
boot_cpu_data.x86_stepping == 0x4))
716716
phys_addr = 36;
717717

718718
size_or_mask = SIZE_OR_MASK_BITS(phys_addr);

‎arch/x86/kernel/cpu/proc.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -72,8 +72,8 @@ static int show_cpuinfo(struct seq_file *m, void *v)
7272
c->x86_model,
7373
c->x86_model_id[0] ? c->x86_model_id : "unknown");
7474

75-
if (c->x86_mask || c->cpuid_level >= 0)
76-
seq_printf(m, "stepping\t: %d\n", c->x86_mask);
75+
if (c->x86_stepping || c->cpuid_level >= 0)
76+
seq_printf(m, "stepping\t: %d\n", c->x86_stepping);
7777
else
7878
seq_puts(m, "stepping\t: unknown\n");
7979
if (c->microcode)

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