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Merge tag 'loongarch-kvm-6.13' of git://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson into HEAD
LoongArch KVM changes for v6.13 1. Add iocsr and mmio bus simulation in kernel. 2. Add in-kernel interrupt controller emulation. 3. Add virt extension support for eiointc irqchip.
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‎.mailmap

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@@ -665,6 +665,7 @@ Tomeu Vizoso <[email protected]> <[email protected]>
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Thomas Graf <[email protected]>
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Thomas Körper <[email protected]> <[email protected]>
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Thomas Pedersen <[email protected]>
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Thorsten Blum <[email protected]> <[email protected]>
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Tiezhu Yang <[email protected]> <[email protected]>
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Tingwei Zhang <[email protected]> <[email protected]>
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Tirupathi Reddy <[email protected]> <[email protected]>

‎CREDITS

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@@ -1204,6 +1204,10 @@ S: Dreisbachstrasse 24
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S: D-57250 Netphen
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S: Germany
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N: Florian Fainelli
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E: [email protected]
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D: DSA
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12071211
N: Rik Faith
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E: [email protected]
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D: Future Domain TMC-16x0 SCSI driver (author)

‎Documentation/admin-guide/kernel-parameters.txt

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@@ -6688,7 +6688,7 @@
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0: no polling (default)
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thp_anon= [KNL]
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Format: <size>,<size>[KMG]:<state>;<size>-<size>[KMG]:<state>
6691+
Format: <size>[KMG],<size>[KMG]:<state>;<size>[KMG]-<size>[KMG]:<state>
66926692
state is one of "always", "madvise", "never" or "inherit".
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Control the default behavior of the system with respect
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to anonymous transparent hugepages.

‎Documentation/admin-guide/mm/transhuge.rst

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@@ -303,7 +303,7 @@ control by passing the parameter ``transparent_hugepage=always`` or
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kernel command line.
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Alternatively, each supported anonymous THP size can be controlled by
306-
passing ``thp_anon=<size>,<size>[KMG]:<state>;<size>-<size>[KMG]:<state>``,
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passing ``thp_anon=<size>[KMG],<size>[KMG]:<state>;<size>[KMG]-<size>[KMG]:<state>``,
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where ``<size>`` is the THP size (must be a power of 2 of PAGE_SIZE and
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supported anonymous THP) and ``<state>`` is one of ``always``, ``madvise``,
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``never`` or ``inherit``.

‎Documentation/arch/loongarch/irq-chip-model.rst

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@@ -85,6 +85,70 @@ to CPUINTC directly::
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| Devices |
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+---------+
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88+
Virtual Extended IRQ model
89+
==========================
90+
91+
In this model, IPI (Inter-Processor Interrupt) and CPU Local Timer interrupt
92+
go to CPUINTC directly, CPU UARTS interrupts go to PCH-PIC, while all other
93+
devices interrupts go to PCH-PIC/PCH-MSI and gathered by V-EIOINTC (Virtual
94+
Extended I/O Interrupt Controller), and then go to CPUINTC directly::
95+
96+
+-----+ +-------------------+ +-------+
97+
| IPI |--> | CPUINTC(0-255vcpu)| <-- | Timer |
98+
+-----+ +-------------------+ +-------+
99+
^
100+
|
101+
+-----------+
102+
| V-EIOINTC |
103+
+-----------+
104+
^ ^
105+
| |
106+
+---------+ +---------+
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| PCH-PIC | | PCH-MSI |
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+---------+ +---------+
109+
^ ^ ^
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| | |
111+
+--------+ +---------+ +---------+
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| UARTs | | Devices | | Devices |
113+
+--------+ +---------+ +---------+
114+
115+
116+
Description
117+
-----------
118+
V-EIOINTC (Virtual Extended I/O Interrupt Controller) is an extension of
119+
EIOINTC, it only works in VM mode which runs in KVM hypervisor. Interrupts can
120+
be routed to up to four vCPUs via standard EIOINTC, however with V-EIOINTC
121+
interrupts can be routed to up to 256 virtual cpus.
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123+
With standard EIOINTC, interrupt routing setting includes two parts: eight
124+
bits for CPU selection and four bits for CPU IP (Interrupt Pin) selection.
125+
For CPU selection there is four bits for EIOINTC node selection, four bits
126+
for EIOINTC CPU selection. Bitmap method is used for CPU selection and
127+
CPU IP selection, so interrupt can only route to CPU0 - CPU3 and IP0-IP3 in
128+
one EIOINTC node.
129+
130+
With V-EIOINTC it supports to route more CPUs and CPU IP (Interrupt Pin),
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there are two newly added registers with V-EIOINTC.
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133+
EXTIOI_VIRT_FEATURES
134+
--------------------
135+
This register is read-only register, which indicates supported features with
136+
V-EIOINTC. Feature EXTIOI_HAS_INT_ENCODE and EXTIOI_HAS_CPU_ENCODE is added.
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Feature EXTIOI_HAS_INT_ENCODE is part of standard EIOINTC. If it is 1, it
139+
indicates that CPU Interrupt Pin selection can be normal method rather than
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bitmap method, so interrupt can be routed to IP0 - IP15.
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142+
Feature EXTIOI_HAS_CPU_ENCODE is entension of V-EIOINTC. If it is 1, it
143+
indicates that CPU selection can be normal method rather than bitmap method,
144+
so interrupt can be routed to CPU0 - CPU255.
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EXTIOI_VIRT_CONFIG
147+
------------------
148+
This register is read-write register, for compatibility intterupt routed uses
149+
the default method which is the same with standard EIOINTC. If the bit is set
150+
with 1, it indicated HW to use normal method rather than bitmap method.
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Advanced Extended IRQ model
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===========================
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‎Documentation/devicetree/bindings/firmware/arm,scmi.yaml

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atomic mode of operation, even if requested.
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default: 0
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max-rx-timeout-ms:
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arm,max-rx-timeout-ms:
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description:
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An optional time value, expressed in milliseconds, representing the
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transport maximum timeout value for the receive channel. The value should

‎Documentation/devicetree/bindings/net/xlnx,axi-ethernet.yaml

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- gmii
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- rgmii
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- sgmii
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- 1000BaseX
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- 1000base-x
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xlnx,phy-type:
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description:

‎Documentation/netlink/specs/mptcp_pm.yaml

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doc: Get endpoint information
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attribute-set: attr
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dont-validate: [ strict ]
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flags: [ uns-admin-perm ]
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do: &get-addr-attrs
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request:
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attributes:

‎Documentation/networking/j1939.rst

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@@ -121,7 +121,7 @@ format, the Group Extension is set in the PS-field.
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On the other hand, when using PDU1 format, the PS-field contains a so-called
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Destination Address, which is _not_ part of the PGN. When communicating a PGN
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from user space to kernel (or vice versa) and PDU2 format is used, the PS-field
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from user space to kernel (or vice versa) and PDU1 format is used, the PS-field
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of the PGN shall be set to zero. The Destination Address shall be set
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elsewhere.
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‎Documentation/translations/zh_CN/arch/loongarch/irq-chip-model.rst

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@@ -87,6 +87,61 @@ PCH-LPC/PCH-MSI，然后被EIOINTC统一收集，再直接到达CPUINTC::
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| Devices |
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+---------+
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虚拟扩展IRQ模型
91+
===============
92+
93+
在这种模型里面, IPI(Inter-Processor Interrupt) 和CPU本地时钟中断直接发送到CPUINTC,
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CPU串口 (UARTs) 中断发送到PCH-PIC, 而其他所有设备的中断则分别发送到所连接的PCH_PIC/
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PCH-MSI, 然后V-EIOINTC统一收集，再直接到达CPUINTC::
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+-----+ +-------------------+ +-------+
98+
| IPI |--> | CPUINTC(0-255vcpu)| <-- | Timer |
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+-----+ +-------------------+ +-------+
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^
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|
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+-----------+
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| V-EIOINTC |
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+-----------+
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^ ^
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| |
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+---------+ +---------+
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| PCH-PIC | | PCH-MSI |
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+---------+ +---------+
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^ ^ ^
111+
| | |
112+
+--------+ +---------+ +---------+
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| UARTs | | Devices | | Devices |
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+--------+ +---------+ +---------+
115+
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V-EIOINTC 是EIOINTC的扩展, 仅工作在虚拟机模式下, 中断经EIOINTC最多可个路由到
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４个虚拟CPU. 但中断经V-EIOINTC最多可个路由到256个虚拟CPU.
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119+
传统的EIOINTC中断控制器，中断路由分为两个部分：8比特用于控制路由到哪个CPU，
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4比特用于控制路由到特定CPU的哪个中断管脚。控制CPU路由的8比特前4比特用于控制
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路由到哪个EIOINTC节点，后4比特用于控制此节点哪个CPU。中断路由在选择CPU路由
122+
和CPU中断管脚路由时，使用bitmap编码方式而不是正常编码方式，所以对于一个
123+
EIOINTC中断控制器节点，中断只能路由到CPU0 - CPU3，中断管脚IP0-IP3。
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125+
V-EIOINTC新增了两个寄存器，支持中断路由到更多CPU个和中断管脚。
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127+
V-EIOINTC功能寄存器
128+
-------------------
129+
功能寄存器是只读寄存器，用于显示V-EIOINTC支持的特性，目前两个支持两个特性
130+
EXTIOI_HAS_INT_ENCODE 和 EXTIOI_HAS_CPU_ENCODE。
131+
132+
特性EXTIOI_HAS_INT_ENCODE是传统EIOINTC中断控制器的一个特性，如果此比特为1，
133+
显示CPU中断管脚路由方式支持正常编码，而不是bitmap编码，所以中断可以路由到
134+
管脚IP0 - IP15。
135+
136+
特性EXTIOI_HAS_CPU_ENCODE是V-EIOINTC新增特性，如果此比特为1，表示CPU路由
137+
方式支持正常编码，而不是bitmap编码，所以中断可以路由到CPU0 - CPU255。
138+
139+
V-EIOINTC配置寄存器
140+
-------------------
141+
配置寄存器是可读写寄存器，为了兼容性考虑，如果不写此寄存器，中断路由采用
142+
和传统EIOINTC相同的路由设置。如果对应比特设置为1，表示采用正常路由方式而
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不是bitmap编码的路由方式。
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高级扩展IRQ模型
91146
===============
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‎MAINTAINERS

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F: drivers/hid/amd-sfh-hid/
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AMD SPI DRIVER
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M: Sanjay R Mehta <[email protected]>
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S: Maintained
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M: Raju Rangoju <[email protected]>
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L: [email protected]
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S: Supported
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F: drivers/spi/spi-amd.c
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AMD XGBE DRIVER
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F: Documentation/devicetree/bindings/bus/qcom*
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F: Documentation/devicetree/bindings/cache/qcom,llcc.yaml
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F: Documentation/devicetree/bindings/reserved-memory/qcom*
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F: Documentation/devicetree/bindings/soc/qcom/
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F: arch/arm/boot/dts/qcom/
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F: arch/arm/configs/qcom_defconfig
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AXI PWM GENERATOR
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M: Michael Hennerich <[email protected]>
37473748
M: Nuno Sá <[email protected]>
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R: Trevor Gamblin <[email protected]>
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S: Supported
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W: https://ez.analog.com/linux-software-drivers
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NETWORKING [DSA]
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M: Andrew Lunn <[email protected]>
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M: Florian Fainelli <[email protected]>
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F: Documentation/devicetree/bindings/net/dsa/
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S: Maintained
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Q: https://patchwork.kernel.org/project/linux-riscv/list/
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T: git https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/
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F: Documentation/devicetree/bindings/riscv/
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F: arch/riscv/boot/dts/
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X: arch/riscv/boot/dts/allwinner/
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X: arch/riscv/boot/dts/renesas/
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X: arch/riscv/boot/dts/sophgo/
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X: arch/riscv/boot/dts/thead/
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F: arch/riscv/boot/dts/canaan/
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F: arch/riscv/boot/dts/microchip/
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F: arch/riscv/boot/dts/sifive/
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F: arch/riscv/boot/dts/starfive/
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RISC-V PMU DRIVERS
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M: Atish Patra <[email protected]>
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W: https://github.com/thesofproject/linux/
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SOUND - GENERIC SOUND CARD (Simple-Audio-Card, Audio-Graph-Card)
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M: Kuninori Morimoto <[email protected]>
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S: Supported
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L: [email protected]
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F: sound/soc/generic/
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F: include/sound/simple_card*
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F: Documentation/devicetree/bindings/sound/simple-card.yaml
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SOUNDWIRE SUBSYSTEM
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M: Bard Liao <[email protected]>

‎Makefile

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VERSION = 6
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PATCHLEVEL = 12
44
SUBLEVEL = 0
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EXTRAVERSION = -rc6
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EXTRAVERSION = -rc7
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NAME = Baby Opossum Posse
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# *DOCUMENTATION*

‎arch/arm/boot/dts/rockchip/rk3036-kylin.dts

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325325
&i2c2 {
326326
status = "okay";
327327

328-
rt5616: rt5616@1b {
329-
compatible = "rt5616";
328+
rt5616: audio-codec@1b {
329+
compatible = "realtek,rt5616";
330330
reg = <0x1b>;
331331
clocks = <&cru SCLK_I2S_OUT>;
332332
clock-names = "mclk";

‎arch/arm/boot/dts/rockchip/rk3036.dtsi

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384384
};
385385
};
386386

387-
acodec: acodec-ana@20030000 {
388-
compatible = "rk3036-codec";
387+
acodec: audio-codec@20030000 {
388+
compatible = "rockchip,rk3036-codec";
389389
reg = <0x20030000 0x4000>;
390-
rockchip,grf = <&grf>;
391390
clock-names = "acodec_pclk";
392391
clocks = <&cru PCLK_ACODEC>;
392+
rockchip,grf = <&grf>;
393+
#sound-dai-cells = <0>;
393394
status = "disabled";
394395
};
395396

@@ -399,7 +400,6 @@
399400
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
400401
clocks = <&cru PCLK_HDMI>;
401402
clock-names = "pclk";
402-
rockchip,grf = <&grf>;
403403
pinctrl-names = "default";
404404
pinctrl-0 = <&hdmi_ctl>;
405405
#sound-dai-cells = <0>;
@@ -553,11 +553,11 @@
553553
};
554554

555555
spi: spi@20074000 {
556-
compatible = "rockchip,rockchip-spi";
556+
compatible = "rockchip,rk3036-spi";
557557
reg = <0x20074000 0x1000>;
558558
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
559-
clocks = <&cru PCLK_SPI>, <&cru SCLK_SPI>;
560-
clock-names = "apb-pclk","spi_pclk";
559+
clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>;
560+
clock-names = "spiclk", "apb_pclk";
561561
dmas = <&pdma 8>, <&pdma 9>;
562562
dma-names = "tx", "rx";
563563
pinctrl-names = "default";

‎arch/arm64/Kconfig

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22142214
bool "ARM Scalable Matrix Extension support"
22152215
default y
22162216
depends on ARM64_SVE
2217+
depends on BROKEN
22172218
help
22182219
The Scalable Matrix Extension (SME) is an extension to the AArch64
22192220
execution state which utilises a substantial subset of the SVE

‎arch/arm64/boot/dts/freescale/imx8-ss-lvds0.dtsi

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -14,26 +14,26 @@ lvds0_subsys: bus@56240000 {
1414
compatible = "fsl,imx8qxp-lpcg";
1515
reg = <0x56243000 0x4>;
1616
#clock-cells = <1>;
17-
clock-output-names = "mipi1_lis_lpcg_ipg_clk";
17+
clock-output-names = "lvds0_lis_lpcg_ipg_clk";
1818
power-domains = <&pd IMX_SC_R_MIPI_1>;
1919
};
2020

2121
qm_lvds0_pwm_lpcg: qxp_mipi1_pwm_lpcg: clock-controller@5624300c {
2222
compatible = "fsl,imx8qxp-lpcg";
2323
reg = <0x5624300c 0x4>;
2424
#clock-cells = <1>;
25-
clock-output-names = "mipi1_pwm_lpcg_clk",
26-
"mipi1_pwm_lpcg_ipg_clk",
27-
"mipi1_pwm_lpcg_32k_clk";
25+
clock-output-names = "lvds0_pwm_lpcg_clk",
26+
"lvds0_pwm_lpcg_ipg_clk",
27+
"lvds0_pwm_lpcg_32k_clk";
2828
power-domains = <&pd IMX_SC_R_MIPI_1_PWM_0>;
2929
};
3030

3131
qm_lvds0_i2c0_lpcg: qxp_mipi1_i2c0_lpcg: clock-controller@56243010 {
3232
compatible = "fsl,imx8qxp-lpcg";
3333
reg = <0x56243010 0x4>;
3434
#clock-cells = <1>;
35-
clock-output-names = "mipi1_i2c0_lpcg_clk",
36-
"mipi1_i2c0_lpcg_ipg_clk";
35+
clock-output-names = "lvds0_i2c0_lpcg_clk",
36+
"lvds0_i2c0_lpcg_ipg_clk";
3737
power-domains = <&pd IMX_SC_R_MIPI_1_I2C_0>;
3838
};
3939

‎arch/arm64/boot/dts/freescale/imx8-ss-vpu.dtsi

Lines changed: 2 additions & 2 deletions
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@@ -15,7 +15,7 @@ vpu: vpu@2c000000 {
1515
mu_m0: mailbox@2d000000 {
1616
compatible = "fsl,imx6sx-mu";
1717
reg = <0x2d000000 0x20000>;
18-
interrupts = <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>;
18+
interrupts = <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>;
1919
#mbox-cells = <2>;
2020
power-domains = <&pd IMX_SC_R_VPU_MU_0>;
2121
status = "disabled";
@@ -24,7 +24,7 @@ vpu: vpu@2c000000 {
2424
mu1_m0: mailbox@2d020000 {
2525
compatible = "fsl,imx6sx-mu";
2626
reg = <0x2d020000 0x20000>;
27-
interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>;
27+
interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>;
2828
#mbox-cells = <2>;
2929
power-domains = <&pd IMX_SC_R_VPU_MU_1>;
3030
status = "disabled";

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