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Alexander Zilberkant
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rewrite linker scripts and addresses part configuration
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‎docs/porting/psa/spm.md

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@@ -7,84 +7,176 @@ For more information about SPM, refer to [TODO: WHEN READY, SPM OVERVIEW PAGE LI
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**This page gives guidelines for silicon partners wishing to have Secure Partition Manager capabilities**
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## Linker Scripts
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## Memory layout
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Typically PSA platforms will share same RAM and flash between secure and non secure cores.
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In order to provide PSA isolation level 1 or higher we need to partition both RAM and flash
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in a way described by following drawing:
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```text
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RAM
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+-----------+-------------+--------------------------------------------------+
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| Secure | Shared | Non-Secure |
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| RAM | RAM | RAM |
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+-----------+-------------+--------------------------------------------------+
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Silicon partners must edit the secure and non-secure linker scripts to define sections for RAM, FLASH and SHARED_RAM.
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Flash
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+-----------------------+----------------------------------------------------+
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| Secure | Non-Secure |
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| Flash | Flash |
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+-----------------------+----------------------------------------------------+
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```
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In order to achieve RAM and Flash partitioning start and size values must be added to target a configuration in `targets.json`.
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The process of defining can be described in the following steps:
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1. secure target must inherit from `SPE_Target` meta-target
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2. non-secure target must inherit from `NSPE_Target`
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3. both targets must override default configuration by specifying flash RAM and shared RAM regions.
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```json
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"FUTURE_SEQUANA_M0_PSA": {
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"inherits": ["SPE_Target", "FUTURE_SEQUANA_M0"],
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"extra_labels_add": ["PSOC6_PSA"],
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"components_add": ["SPM_MAILBOX"],
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"macros_add": ["PSOC6_DYNSRM_DISABLE=1"],
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"deliver_to_target": "FUTURE_SEQUANA_PSA",
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"overrides": {
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"secure-rom-start": "0x10000000",
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"secure-rom-size": "0x78000",
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"non-secure-rom-start": "0x10080000",
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"non-secure-rom-size": "0x78000",
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"secure-ram-start": "0x08000000",
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"secure-ram-size": "0x10000",
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"non-secure-ram-start": "0x08011000",
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"non-secure-ram-size": "0x36800",
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"shared-ram-start": "0x08010000",
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"shared-ram-size": "0x1000"
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}
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},
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"FUTURE_SEQUANA_PSA": {
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"inherits": ["NSPE_Target", "FUTURE_SEQUANA"],
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"sub_target": "FUTURE_SEQUANA_M0_PSA",
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"extra_labels_remove": ["CORDIO"],
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"extra_labels_add": ["PSOC6_PSA"],
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"components_add": ["SPM_MAILBOX"],
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"macros_add": ["PSOC6_DYNSRM_DISABLE=1"],
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"overrides": {
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"secure-rom-start": "0x10000000",
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"secure-rom-size": "0x78000",
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"non-secure-rom-start": "0x10080000",
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"non-secure-rom-size": "0x78000",
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"secure-ram-start": "0x08000000",
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"secure-ram-size": "0x10000",
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"non-secure-ram-start": "0x08011000",
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"non-secure-ram-size": "0x36800",
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"shared-ram-start": "0x08010000",
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"shared-ram-size": "0x1000"
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}
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}
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```
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Linker scripts guidelines:
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- *__shared_memory_start* symbol is used in SPM code so it must be set with the start address of the shared memory
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- *__shared_memory_start* must be 4 bytes aligned
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- *__shared_memory_end* symbol is used in SPM code so it must be set with the end address of the shared memory
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- SHARED_RAM must have Read/Write permissions from secure and non-secure cores
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- SHARED_RAM address must be 4 bytes aligned
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- SHARED_RAM must be given a minimum memory space of 256 bytes
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- Secure RAM base address must be 4 bytes aligned and have Read/Write permissions only from secure core
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- Secure FLASH base address must be 4 bytes aligned and have Read/Write/Execute permissions only from secure core
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- Non-Secure RAM base address must be 4 bytes aligned and have Read/Write permissions from secure and non-secure cores
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- Non-Secure FLASH base address must be 4 bytes aligned; must have Read permissions from secure and non-secure cores, and Execute permissions from non-secure core; May have Write permissions from secure and non-secure cores
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> Note: shared memory region is required only for multi core architectures.
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This is an example of the relevant parts inside the linker scripts:
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## Linker Scripts
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#### SECURE Core Linker Script
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Linker scripts mast include `MBED_ROM_START`, `MBED_ROM_SIZE`, `MBED_RAM_START` and `MBED_RAM_START` macros for defining memory regions.
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Shared memory region is defined by reserving RAM space for shared memory usage. Shared memory location is target specific and depends on the memory protection scheme applied.
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Typically shared memory will be located before/after non-secure RAM, for saving MPU regions. Shared memory region is considered non-secure memory used by both cores.
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### Linker Script example GCC_ARM
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```
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...
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...
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MEMORY
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{
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/* The ram and flash regions control RAM and flash memory allocation for the SECURE core.
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* You can change the memory allocation by editing the 'ram' and 'flash' regions.
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* Your changes must be aligned with the corresponding memory regions for the NON-SECURE core in the
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* NON-SECURE linker script.
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*/
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ram (rwx) : ORIGIN = 0x08000000, LENGTH = 0x10000
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shared_ram (rw) : ORIGIN = 0x08010000, LENGTH = 0x1000
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flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x78000
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...
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...
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}
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#if !defined(MBED_ROM_START)
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#define MBED_ROM_START 0x10000000
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#endif
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...
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...
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#if !defined(MBED_ROM_SIZE)
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#define MBED_ROM_SIZE 0x78000
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#endif
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/* .shared_mem section contains memory shared between SECURE core and NON-SECURE core */
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.shared_mem :
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{
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__shared_memory_start = .;
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. += 0x1000;
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__shared_memory_end = .;
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#if !defined(MBED_RAM_START)
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#define MBED_RAM_START 0x08000000
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#endif
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/* Check if section is 4 bytes aligned */
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ASSERT (((__shared_memory_start % 4) == 0), "Error: shared_mem section is not 4 bytes aligned!!");
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} > shared_ram
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#if !defined(MBED_RAM_SIZE)
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#define MBED_RAM_SIZE 0x10000
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#endif
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...
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/* The MEMORY section below describes the location and size of blocks of memory in the target.
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* Use this section to specify the memory regions available for allocation.
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*/
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MEMORY
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{
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ram (rwx) : ORIGIN = MBED_RAM_START, LENGTH = MBED_RAM_SIZE
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flash (rx) : ORIGIN = MBED_ROM_START, LENGTH = MBED_ROM_SIZE
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}
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...
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```
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### Linker Script example ARM
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#### NON-SECURE Core Linker Script
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```
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...
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...
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MEMORY
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{
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/* The ram and flash regions control RAM and flash memory allocation for the NON-SECURE core.
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* You can change the memory allocation by editing the 'ram' and 'flash' regions.
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* Your changes must be aligned with the corresponding memory regions for the SECURE core in the
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* SECURE linker script.
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*/
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ram (rwx) : ORIGIN = 0x08011000, LENGTH = 0x36800
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flash (rx) : ORIGIN = 0x10080000, LENGTH = 0x78000
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...
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...
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#if !defined(MBED_ROM_START)
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#define MBED_ROM_START 0x10000000
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#endif
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#if !defined(MBED_ROM_SIZE)
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#define MBED_ROM_SIZE 0x78000
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#endif
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#if !defined(MBED_RAM_START)
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#define MBED_RAM_START 0x08000000
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#endif
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#if !defined(MBED_RAM_SIZE)
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#define MBED_RAM_SIZE 0x10000
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#endif
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#define MBED_RAM0_START MBED_RAM_START
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#define MBED_RAM0_SIZE 0x100
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#define MBED_RAM1_START (MBED_RAM_START + MBED_RAM0_SIZE)
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#define MBED_RAM1_SIZE (MBED_RAM_SIZE - MBED_RAM0_SIZE)
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LR_IROM1 MBED_ROM_START MBED_ROM_SIZE {
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ER_IROM1 MBED_ROM_START MBED_ROM_SIZE {
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*.o (RESET, +First)
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*(InRoot$$Sections)
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.ANY (+RO)
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}
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RW_IRAM0 MBED_RAM0_START UNINIT MBED_RAM0_SIZE { ;no init section
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*(*nvictable)
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}
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RW_IRAM1 MBED_RAM1_START MBED_RAM1_SIZE {
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.ANY (+RW +ZI)
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}
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}
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```
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### Linker Script example IAR
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...
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...
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```
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if (!isdefinedsymbol(MBED_ROM_START)) {
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define symbol MBED_ROM_START = 0x10000000;
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}
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if (!isdefinedsymbol(MBED_ROM_SIZE)) {
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define symbol MBED_ROM_SIZE = 0x78000;
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}
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if (!isdefinedsymbol(MBED_RAM_START)) {
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define symbol MBED_RAM_START = 0x08000000;
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}
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if (!isdefinedsymbol(MBED_RAM_SIZE)) {
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define symbol MBED_RAM_SIZE = 0x10000;
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}
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/* RAM */
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define symbol __ICFEDIT_region_IRAM1_start__ = MBED_RAM_START;
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define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE);
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/* Flash */
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define symbol __ICFEDIT_region_IROM1_start__ = MBED_ROM_START;
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define symbol __ICFEDIT_region_IROM1_end__ = (MBED_ROM_START + MBED_ROM_SIZE);
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...
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```
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## Mailbox
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@@ -115,10 +207,7 @@ Target specific code of silicon partners who wish to have SPM capabilities must:
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- Implement a list of functions which are being called by SPM code
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- Call other functions supplied by ARM
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The HAL can be logically divided into 3 different fields:
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#### Addresses
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This part of HAL allows the silicon partner to share the addresses set in the linker scripts with the SPM code. The SPM uses these addresses mostly to enforce access permissions.
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The HAL can be logically divided into 2 different fields:
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#### Mailbox
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This part of HAL allows the silicon partner to implement a thin layer of the mailbox mechanism which is specific to their platform.

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