|
| 1 | +#if !DEVICE_QSPI |
| 2 | +#error [NOT_SUPPORTED] QSPI not supported for this target |
| 3 | +#endif |
| 4 | + |
| 5 | +#include "mbed.h" |
| 6 | +#include "drivers/QSPI.h" |
| 7 | + |
| 8 | +#define CMD_WRITE 0x02 |
| 9 | +#define CMD_READ 0x03 |
| 10 | +#define CMD_ERASE 0x20 |
| 11 | +#define CMD_RDSR 0x5 |
| 12 | +#define CMD_WREN 0x6 |
| 13 | +#define CMD_RSTEN 0x66 |
| 14 | +#define CMD_RST 0x99 |
| 15 | +#define STATUS_REG_SIZE 2 |
| 16 | +#define BIT_WIP 0x1 |
| 17 | +#define BIT_WEL 0x2 |
| 18 | +#define BUF_SIZE 10 |
| 19 | + |
| 20 | +// hardware ssel (where applicable) |
| 21 | +QSPI qspi_device(QSPI_FLASH1_IO0, QSPI_FLASH1_IO1, QSPI_FLASH1_IO2, QSPI_FLASH1_IO3, QSPI_FLASH1_SCK, QSPI_FLASH1_CSN); // io0, io1, io2, io3, sclk, ssel |
| 22 | + |
| 23 | +static bool mem_ready() |
| 24 | +{ |
| 25 | + char status_value[STATUS_REG_SIZE] = {0xFF}; |
| 26 | + int retries = 10000; |
| 27 | + bool mem_ready = true; |
| 28 | + |
| 29 | + do { |
| 30 | + retries--; |
| 31 | + if (QSPI_STATUS_OK != qspi_device.command_transfer(CMD_RDSR, -1, NULL, 0, status_value, STATUS_REG_SIZE)) { |
| 32 | + printf("Reading Status Register failed \n"); |
| 33 | + } |
| 34 | + wait_ms(1); |
| 35 | + } while ( (status_value[0] & BIT_WIP) != 0 && retries); |
| 36 | + |
| 37 | + if ((status_value[0] & BIT_WIP) != 0) { |
| 38 | + printf ("mem_ready FALSE: status value = 0x%x\n", (int)status_value[0]); |
| 39 | + mem_ready = false; |
| 40 | + } |
| 41 | + return mem_ready; |
| 42 | +} |
| 43 | + |
| 44 | +static int write_enable() |
| 45 | +{ |
| 46 | + char status_value[STATUS_REG_SIZE] = {0}; |
| 47 | + int status = -1; |
| 48 | + |
| 49 | + if (QSPI_STATUS_OK != qspi_device.command_transfer(CMD_WREN, -1, NULL, 0, NULL, 0)) { |
| 50 | + printf("Sending WREN command FAILED \n"); |
| 51 | + return status; |
| 52 | + } |
| 53 | + |
| 54 | + if ( false == mem_ready()) { |
| 55 | + printf("Device not ready \n"); |
| 56 | + return status; |
| 57 | + } |
| 58 | + |
| 59 | + if (QSPI_STATUS_OK != qspi_device.command_transfer(CMD_RDSR, -1, NULL, 0, status_value, STATUS_REG_SIZE)) { |
| 60 | + printf("Reading Status Register failed \n"); |
| 61 | + return status; |
| 62 | + } |
| 63 | + |
| 64 | + if ((status_value[0] & BIT_WEL)) { |
| 65 | + status = 0; |
| 66 | + } |
| 67 | + return status; |
| 68 | +} |
| 69 | + |
| 70 | +static int flash_init() |
| 71 | +{ |
| 72 | + int status = QSPI_STATUS_OK; |
| 73 | + char status_value[STATUS_REG_SIZE] = {0}; |
| 74 | + |
| 75 | + // Read the Status Register from device |
| 76 | + status = qspi_device.command_transfer(CMD_RDSR, -1, NULL, 0, status_value, STATUS_REG_SIZE); |
| 77 | + if (status != QSPI_STATUS_OK) { |
| 78 | + printf("Reading Status Register failed: value = 0x%x\n", (int)status_value[0]); |
| 79 | + return status; |
| 80 | + } |
| 81 | + |
| 82 | + // Send Reset Enable |
| 83 | + status = qspi_device.command_transfer(CMD_RSTEN, -1, NULL, 0, NULL, 0); |
| 84 | + if (status == QSPI_STATUS_OK) { |
| 85 | + printf("Sending RSTEN Success \n"); |
| 86 | + } else { |
| 87 | + printf("Sending RSTEN failed \n"); |
| 88 | + return status; |
| 89 | + } |
| 90 | + |
| 91 | + if ( false == mem_ready()) { |
| 92 | + printf("Device not ready \n"); |
| 93 | + return -1; |
| 94 | + } |
| 95 | + |
| 96 | + // Send Reset |
| 97 | + status = qspi_device.command_transfer(CMD_RST, -1, NULL, 0, NULL, 0); |
| 98 | + if (status == QSPI_STATUS_OK) { |
| 99 | + printf("Sending RST Success \n"); |
| 100 | + } else { |
| 101 | + printf("Sending RST failed \n"); |
| 102 | + return status; |
| 103 | + } |
| 104 | + |
| 105 | + if ( false == mem_ready()) { |
| 106 | + printf("Device not ready \n"); |
| 107 | + return -1; |
| 108 | + } |
| 109 | + return status; |
| 110 | +} |
| 111 | + |
| 112 | +static int sector_erase(unsigned int flash_addr) |
| 113 | +{ |
| 114 | + if (0 != write_enable()) { |
| 115 | + printf("Write Enabe failed \n"); |
| 116 | + return -1; |
| 117 | + } |
| 118 | + |
| 119 | + if( QSPI_STATUS_OK!= qspi_device.command_transfer(CMD_ERASE, (((int)flash_addr) & 0x00FFF000), NULL, 0, NULL, 0)) |
| 120 | + { |
| 121 | + printf("Erase failed\n"); |
| 122 | + return -1; |
| 123 | + } |
| 124 | + |
| 125 | + if ( false == mem_ready()) { |
| 126 | + printf("Device not ready \n"); |
| 127 | + return -1; |
| 128 | + } |
| 129 | + |
| 130 | + return 0; |
| 131 | +} |
| 132 | + |
| 133 | +int main() { |
| 134 | + char tx_buf[] = { 'h', 'e', 'l', 'l', 'o', '\0' }; |
| 135 | + char rx_buf[BUF_SIZE] = {0}; |
| 136 | + size_t buf_len = sizeof(tx_buf); |
| 137 | + qspi_status_t result; |
| 138 | + uint32_t address = 0x1000; |
| 139 | + |
| 140 | + result = qspi_device.configure_format(QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_SINGLE, |
| 141 | + QSPI_CFG_ADDR_SIZE_24, QSPI_CFG_BUS_SINGLE, |
| 142 | + QSPI_CFG_ALT_SIZE_8, QSPI_CFG_BUS_SINGLE, 0); |
| 143 | + if (result != QSPI_STATUS_OK) { |
| 144 | + printf("Config format failed\n"); |
| 145 | + } |
| 146 | + |
| 147 | + if (QSPI_STATUS_OK != flash_init()) { |
| 148 | + printf ("Init failed\n"); |
| 149 | + return -1; |
| 150 | + } |
| 151 | + |
| 152 | + if (0 != sector_erase(address)) { |
| 153 | + return -1; |
| 154 | + } |
| 155 | + |
| 156 | + if (0 != write_enable()) { |
| 157 | + printf("Write Enabe failed \n"); |
| 158 | + return -1; |
| 159 | + } |
| 160 | + result = qspi_device.write(CMD_WRITE, -1, address, tx_buf, &buf_len); |
| 161 | + if (result != QSPI_STATUS_OK) { |
| 162 | + printf("Write failed\n"); |
| 163 | + return result; |
| 164 | + } |
| 165 | + printf("Write done: %s \n", tx_buf); |
| 166 | + |
| 167 | + if ( false == mem_ready()) { |
| 168 | + printf("Device not ready \n"); |
| 169 | + return -1; |
| 170 | + } |
| 171 | + |
| 172 | + result = qspi_device.read(CMD_READ, -1, address, rx_buf, &buf_len); |
| 173 | + if (result != QSPI_STATUS_OK) { |
| 174 | + printf("Read failed\n"); |
| 175 | + return result; |
| 176 | + } |
| 177 | + printf ("Data Read = %s\n", rx_buf); |
| 178 | + return 0; |
| 179 | +} |
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