Merge pull request #7875 from c1728p9/feature_CMSIS_5_0b521765

Update CMSIS to 5.4.0

Author: Cruz Monrreal

TESTS/mbedmicro-rtos-mbed/MemoryPool/main.cpp

@@ -450,38 +450,6 @@ void test_mem_pool_free_realloc_first_complex(AllocType atype)
     }
 }
 
-/* Robustness checks for free() function.
- *
- * Given block from the MemoryPool has been successfully deallocated.
- * When free operation is executed on this block again.
- * Then operation fails with osErrorResource status.
- *
- * */
-void test_mem_pool_free_on_freed_block()
-{
-    MemoryPool<int, 1> mem_pool;
-    int *p_block;
-    osStatus status;
-
-    /* Allocate memory block. */
-    p_block = mem_pool.alloc();
-
-    /* Show that memory pool block has been allocated. */
-    TEST_ASSERT_NOT_NULL(p_block);
-
-    /* Free memory block. */
-    status = mem_pool.free(p_block);
-
-    /* Check operation status. */
-    TEST_ASSERT_EQUAL(osOK, status);
-
-    /* Free memory block again. */
-    status = mem_pool.free(p_block);
-
-    /* Check operation status. */
-    TEST_ASSERT_EQUAL(osErrorResource, status);
-}
-
 /* Robustness checks for free() function.
  * Function under test is called with invalid parameters.
  *
@@ -601,7 +569,6 @@ Case cases[] = {
 
     Case("Test: fail (out of free blocks).", test_mem_pool_alloc_fail_wrapper<int, 3>),
 
-    Case("Test: free() - robust (free block twice).", test_mem_pool_free_on_freed_block),
     Case("Test: free() - robust (free called with invalid param - NULL).", free_block_invalid_parameter_null),
     Case("Test: free() - robust (free called with invalid param).", free_block_invalid_parameter)
 };

TESTS/mbedmicro-rtos-mbed/mail/main.cpp

@@ -267,28 +267,6 @@ void test_free_null()
     TEST_ASSERT_EQUAL(osErrorParameter, status);
 }
 
-/** Test same message memory deallocation twice
-
-    Given an empty mailbox
-    Then allocate message memory
-    When try to free it second time
-    Then it return appropriate error code
- */
-void test_free_twice()
-{
-    osStatus status;
-    Mail<uint32_t, 4> mail_box;
-
-    uint32_t *mail = mail_box.alloc();
-    TEST_ASSERT_NOT_EQUAL(NULL, mail);
-
-    status = mail_box.free(mail);
-    TEST_ASSERT_EQUAL(osOK, status);
-
-    status = mail_box.free(mail);
-    TEST_ASSERT_EQUAL(osErrorResource, status);
-}
-
 /** Test get from empty mailbox with timeout set
 
     Given an empty mailbox
@@ -517,7 +495,6 @@ Case cases[] = {
     Case("Test message send order", test_order),
     Case("Test get with timeout on empty mailbox", test_get_empty_timeout),
     Case("Test get without timeout on empty mailbox", test_get_empty_no_timeout),
-    Case("Test message free twice", test_free_twice),
     Case("Test null message free", test_free_null),
     Case("Test invalid message free", test_free_wrong),
     Case("Test message send/receive single thread and order", test_single_thread_order),

cmsis/TARGET_CORTEX_A/cmsis_gcc.h

@@ -1,11 +1,11 @@
 /**************************************************************************//**
  * @file     cmsis_gcc.h
  * @brief    CMSIS compiler specific macros, functions, instructions
- * @version  V1.0.1
- * @date     07. Sep 2017
+ * @version  V1.0.2
+ * @date     09. April 2018
  ******************************************************************************/
 /*
- * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -450,7 +450,9 @@ __STATIC_FORCEINLINE  uint32_t __get_FPSCR(void)
 {
   #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
        (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
-  #if __has_builtin(__builtin_arm_get_fpscr) || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+  #if __has_builtin(__builtin_arm_get_fpscr) 
+  // Re-enable using built-in when GCC has been fixed
+  // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
     /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
     return __builtin_arm_get_fpscr();
   #else
@@ -473,7 +475,9 @@ __STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)
 {
   #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
        (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
-  #if __has_builtin(__builtin_arm_set_fpscr) || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+  #if __has_builtin(__builtin_arm_set_fpscr)
+  // Re-enable using built-in when GCC has been fixed
+  // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
     /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
     __builtin_arm_set_fpscr(fpscr);
   #else

cmsis/TARGET_CORTEX_A/cmsis_iccarm.h

@@ -1,8 +1,8 @@
 /**************************************************************************//**
  * @file     cmsis_iccarm.h
  * @brief    CMSIS compiler ICCARM (IAR Compiler for Arm) header file
- * @version  V5.0.5
- * @date     10. January 2018
+ * @version  V5.0.6
+ * @date     02. March 2018
  ******************************************************************************/
 
 //------------------------------------------------------------------------------

cmsis/TARGET_CORTEX_A/core_ca.h

@@ -1,8 +1,8 @@
 /**************************************************************************//**
  * @file     core_ca.h
  * @brief    CMSIS Cortex-A Core Peripheral Access Layer Header File
- * @version  V1.00
- * @date     22. Feb 2017
+ * @version  V1.0.1
+ * @date     07. May 2018
  ******************************************************************************/
 /*
  * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
@@ -1284,8 +1284,6 @@ __STATIC_INLINE void GIC_SetPendingIRQ(IRQn_Type IRQn)
   } else {
     // INTID 0-15 Software Generated Interrupt
     GICDistributor->SPENDSGIR[IRQn / 4U] = 1U << ((IRQn % 4U) * 8U);
-    // Forward the interrupt to the CPU interface that requested it
-    GICDistributor->SGIR = (IRQn | 0x02000000U);
   }
 }
 

cmsis/TARGET_CORTEX_M/cmsis_armcc.h

@@ -337,8 +337,6 @@ __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
            (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
 
 
-#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
-
 /**
   \brief   Get FPSCR
   \details Returns the current value of the Floating Point Status/Control register.
@@ -372,9 +370,6 @@ __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
 #endif
 }
 
-#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
-
-
 
 /*@} end of CMSIS_Core_RegAccFunctions */
 

cmsis/TARGET_CORTEX_M/cmsis_armclang.h

@@ -237,7 +237,7 @@ __STATIC_FORCEINLINE uint32_t __get_xPSR(void)
  */
 __STATIC_FORCEINLINE uint32_t __get_PSP(void)
 {
-  register uint32_t result;
+  uint32_t result;
 
   __ASM volatile ("MRS %0, psp"  : "=r" (result) );
   return(result);
@@ -252,7 +252,7 @@ __STATIC_FORCEINLINE uint32_t __get_PSP(void)
  */
 __STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
 {
-  register uint32_t result;
+  uint32_t result;
 
   __ASM volatile ("MRS %0, psp_ns"  : "=r" (result) );
   return(result);
@@ -291,7 +291,7 @@ __STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
  */
 __STATIC_FORCEINLINE uint32_t __get_MSP(void)
 {
-  register uint32_t result;
+  uint32_t result;
 
   __ASM volatile ("MRS %0, msp" : "=r" (result) );
   return(result);
@@ -306,7 +306,7 @@ __STATIC_FORCEINLINE uint32_t __get_MSP(void)
  */
 __STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
 {
-  register uint32_t result;
+  uint32_t result;
 
   __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
   return(result);
@@ -346,7 +346,7 @@ __STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
  */
 __STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
 {
-  register uint32_t result;
+  uint32_t result;
 
   __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
   return(result);
@@ -581,7 +581,7 @@ __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
     // without main extensions, the non-secure PSPLIM is RAZ/WI
   return 0U;
 #else
-  register uint32_t result;
+  uint32_t result;
   __ASM volatile ("MRS %0, psplim"  : "=r" (result) );
   return result;
 #endif
@@ -603,7 +603,7 @@ __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
   // without main extensions, the non-secure PSPLIM is RAZ/WI
   return 0U;
 #else
-  register uint32_t result;
+  uint32_t result;
   __ASM volatile ("MRS %0, psplim_ns"  : "=r" (result) );
   return result;
 #endif
@@ -669,7 +669,7 @@ __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
   // without main extensions, the non-secure MSPLIM is RAZ/WI
   return 0U;
 #else
-  register uint32_t result;
+  uint32_t result;
   __ASM volatile ("MRS %0, msplim" : "=r" (result) );
   return result;
 #endif
@@ -691,7 +691,7 @@ __STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
   // without main extensions, the non-secure MSPLIM is RAZ/WI
   return 0U;
 #else
-  register uint32_t result;
+  uint32_t result;
   __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
   return result;
 #endif
@@ -742,10 +742,6 @@ __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
 #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
            (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
 
-
-#if ((defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
-     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
-
 /**
   \brief   Get FPSCR
   \details Returns the current value of the Floating Point Status/Control register.
@@ -770,10 +766,6 @@ __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
 #define __set_FPSCR(x)      ((void)(x))
 #endif
 
-#endif /* ((defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
-           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
-
-
 
 /*@} end of CMSIS_Core_RegAccFunctions */