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mmahadevan108adbridge
mmahadevan108
authored and
adbridge
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MCUXpresso: Update the Kinetis Serial driver for MBED_TICKLESS
We should not block in case the UART is busy transmitting. The API has been updated to check the status of all UART's and return 1 in case any of them is busy transmitting. Signed-off-by: Mahesh Mahadevan <[email protected]>
1 parent de6ce27 commit 0206f48

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10 files changed

+404
-51
lines changed

10 files changed

+404
-51
lines changed

‎targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/serial_api.c

Lines changed: 46 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -37,7 +37,6 @@ static UART_Type *const uart_addrs[] = UART_BASE_PTRS;
3737
/* Array of UART bus clock frequencies */
3838
static clock_name_t const uart_clocks[] = UART_CLOCK_FREQS;
3939

40-
4140
int stdio_uart_inited = 0;
4241
serial_t stdio_uart;
4342

@@ -340,14 +339,55 @@ const PinMap *serial_rts_pinmap()
340339
return PinMap_UART_RTS;
341340
}
342341

343-
void serial_wait_tx_complete(uint32_t uart_index)
342+
static int serial_is_enabled(uint32_t uart_index)
343+
{
344+
int clock_enabled = 0;
345+
switch (uart_index) {
346+
case 0:
347+
clock_enabled = (SIM->SCGC4 & SIM_SCGC4_UART0_MASK) >> SIM_SCGC4_UART0_SHIFT;
348+
break;
349+
case 1:
350+
clock_enabled = (SIM->SCGC4 & SIM_SCGC4_UART1_MASK) >> SIM_SCGC4_UART1_SHIFT;
351+
break;
352+
case 2:
353+
clock_enabled = (SIM->SCGC4 & SIM_SCGC4_UART2_MASK) >> SIM_SCGC4_UART2_SHIFT;
354+
break;
355+
case 3:
356+
clock_enabled = (SIM->SCGC4 & SIM_SCGC4_UART3_MASK) >> SIM_SCGC4_UART3_SHIFT;
357+
break;
358+
case 4:
359+
clock_enabled = (SIM->SCGC1 & SIM_SCGC1_UART4_MASK) >> SIM_SCGC1_UART4_SHIFT;
360+
break;
361+
default:
362+
break;
363+
}
364+
365+
return clock_enabled;
366+
}
367+
368+
bool serial_check_tx_ongoing()
344369
{
345-
UART_Type *base = uart_addrs[uart_index];
370+
UART_Type *base;
371+
int i;
372+
bool uart_tx_ongoing = false;
373+
374+
for (i = 0; i < FSL_FEATURE_SOC_UART_COUNT; i++) {
375+
/* First check if UART is enabled */
376+
if (!serial_is_enabled(i)) {
377+
/* UART is not enabled, check the next instance */
378+
continue;
379+
}
346380

347-
/* Wait till data is flushed out of transmit buffer */
348-
while (!(kUART_TransmissionCompleteFlag & UART_GetStatusFlags((UART_Type *)base)))
349-
{
381+
base = uart_addrs[i];
382+
383+
/* Check if data is waiting to be written out of transmit buffer */
384+
if (!(kUART_TransmissionCompleteFlag & UART_GetStatusFlags((UART_Type *)base))) {
385+
uart_tx_ongoing = true;
386+
break;
387+
}
350388
}
389+
390+
return uart_tx_ongoing;
351391
}
352392

353393
#endif

‎targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/serial_api.c

Lines changed: 46 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -332,14 +332,55 @@ const PinMap *serial_rts_pinmap()
332332
return PinMap_UART_RTS;
333333
}
334334

335-
void serial_wait_tx_complete(uint32_t uart_index)
335+
static int serial_is_enabled(uint32_t uart_index)
336336
{
337-
LPUART_Type *base = uart_addrs[uart_index];
337+
int clock_enabled = 0;
338+
switch (uart_index) {
339+
case 0:
340+
clock_enabled = (SIM->SCGC2 & SIM_SCGC2_LPUART0_MASK) >> SIM_SCGC2_LPUART0_SHIFT;
341+
break;
342+
case 1:
343+
clock_enabled = (SIM->SCGC2 & SIM_SCGC2_LPUART1_MASK) >> SIM_SCGC2_LPUART1_SHIFT;
344+
break;
345+
case 2:
346+
clock_enabled = (SIM->SCGC2 & SIM_SCGC2_LPUART2_MASK) >> SIM_SCGC2_LPUART2_SHIFT;
347+
break;
348+
case 3:
349+
clock_enabled = (SIM->SCGC2 & SIM_SCGC2_LPUART3_MASK) >> SIM_SCGC2_LPUART3_SHIFT;
350+
break;
351+
case 4:
352+
clock_enabled = (SIM->SCGC2 & SIM_SCGC2_LPUART4_MASK) >> SIM_SCGC2_LPUART4_SHIFT;
353+
break;
354+
default:
355+
break;
356+
}
338357

339-
/* Wait till data is flushed out of transmit buffer */
340-
while (!(kLPUART_TransmissionCompleteFlag & LPUART_GetStatusFlags((LPUART_Type *)base)))
341-
{
358+
return clock_enabled;
359+
}
360+
361+
bool serial_check_tx_ongoing()
362+
{
363+
LPUART_Type *base;
364+
int i;
365+
bool uart_tx_ongoing = false;
366+
367+
for (i = 0; i < FSL_FEATURE_SOC_LPUART_COUNT; i++) {
368+
/* First check if UART is enabled */
369+
if (!serial_is_enabled(i)) {
370+
/* UART is not enabled, check the next instance */
371+
continue;
372+
}
373+
374+
base = uart_addrs[i];
375+
376+
/* Check if data is waiting to be written out of transmit buffer */
377+
if (!(kLPUART_TransmissionCompleteFlag & LPUART_GetStatusFlags((LPUART_Type *)base))) {
378+
uart_tx_ongoing = true;
379+
break;
380+
}
342381
}
382+
383+
return uart_tx_ongoing;
343384
}
344385

345386
#endif

‎targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL27Z/serial_api.c

Lines changed: 37 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -288,14 +288,46 @@ const PinMap *serial_rts_pinmap()
288288
return PinMap_UART_RTS;
289289
}
290290

291-
void serial_wait_tx_complete(uint32_t uart_index)
291+
static int serial_is_enabled(uint32_t uart_index)
292292
{
293-
LPUART_Type *base = uart_addrs[uart_index];
293+
int clock_enabled = 0;
294+
switch (uart_index) {
295+
case 0:
296+
clock_enabled = (SIM->SCGC5 & SIM_SCGC5_LPUART0_MASK) >> SIM_SCGC5_LPUART0_SHIFT;
297+
break;
298+
case 1:
299+
clock_enabled = (SIM->SCGC5 & SIM_SCGC5_LPUART1_MASK) >> SIM_SCGC5_LPUART1_SHIFT;
300+
break;
301+
default:
302+
break;
303+
}
294304

295-
/* Wait till data is flushed out of transmit buffer */
296-
while (!(kLPUART_TransmissionCompleteFlag & LPUART_GetStatusFlags((LPUART_Type *)base)))
297-
{
305+
return clock_enabled;
306+
}
307+
308+
bool serial_check_tx_ongoing()
309+
{
310+
LPUART_Type *base;
311+
int i;
312+
bool uart_tx_ongoing = false;
313+
314+
for (i = 0; i < FSL_FEATURE_SOC_LPUART_COUNT; i++) {
315+
/* First check if UART is enabled */
316+
if (!serial_is_enabled(i)) {
317+
/* UART is not enabled, check the next instance */
318+
continue;
319+
}
320+
321+
base = uart_addrs[i];
322+
323+
/* Check if data is waiting to be written out of transmit buffer */
324+
if (!(kLPUART_TransmissionCompleteFlag & LPUART_GetStatusFlags((LPUART_Type *)base))) {
325+
uart_tx_ongoing = true;
326+
break;
327+
}
298328
}
329+
330+
return uart_tx_ongoing;
299331
}
300332

301333
#endif

‎targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL43Z/serial_api.c

Lines changed: 37 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -300,14 +300,46 @@ const PinMap *serial_rts_pinmap()
300300
return PinMap_UART_RTS;
301301
}
302302

303-
void serial_wait_tx_complete(uint32_t uart_index)
303+
static int serial_is_enabled(uint32_t uart_index)
304304
{
305-
LPUART_Type *base = uart_addrs[uart_index];
305+
int clock_enabled = 0;
306+
switch (uart_index) {
307+
case 0:
308+
clock_enabled = (SIM->SCGC5 & SIM_SCGC5_LPUART0_MASK) >> SIM_SCGC5_LPUART0_SHIFT;
309+
break;
310+
case 1:
311+
clock_enabled = (SIM->SCGC5 & SIM_SCGC5_LPUART1_MASK) >> SIM_SCGC5_LPUART1_SHIFT;
312+
break;
313+
default:
314+
break;
315+
}
306316

307-
/* Wait till data is flushed out of transmit buffer */
308-
while (!(kLPUART_TransmissionCompleteFlag & LPUART_GetStatusFlags((LPUART_Type *)base)))
309-
{
317+
return clock_enabled;
318+
}
319+
320+
bool serial_check_tx_ongoing()
321+
{
322+
LPUART_Type *base;
323+
int i;
324+
bool uart_tx_ongoing = false;
325+
326+
for (i = 0; i < FSL_FEATURE_SOC_LPUART_COUNT; i++) {
327+
/* First check if UART is enabled */
328+
if (!serial_is_enabled(i)) {
329+
/* UART is not enabled, check the next instance */
330+
continue;
331+
}
332+
333+
base = uart_addrs[i];
334+
335+
/* Check if data is waiting to be written out of transmit buffer */
336+
if (!(kLPUART_TransmissionCompleteFlag & LPUART_GetStatusFlags((LPUART_Type *)base))) {
337+
uart_tx_ongoing = true;
338+
break;
339+
}
310340
}
341+
342+
return uart_tx_ongoing;
311343
}
312344

313345
#endif

‎targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/serial_api.c

Lines changed: 40 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -328,14 +328,49 @@ const PinMap *serial_rts_pinmap()
328328
return PinMap_UART_RTS;
329329
}
330330

331-
void serial_wait_tx_complete(uint32_t uart_index)
331+
static int serial_is_enabled(uint32_t uart_index)
332332
{
333-
LPUART_Type *base = uart_addrs[uart_index];
333+
int clock_enabled = 0;
334+
switch (uart_index) {
335+
case 0:
336+
clock_enabled = (SIM->SCGC5 & SIM_SCGC5_LPUART0_MASK) >> SIM_SCGC5_LPUART0_SHIFT;
337+
break;
338+
case 1:
339+
clock_enabled = (SIM->SCGC5 & SIM_SCGC5_LPUART1_MASK) >> SIM_SCGC5_LPUART1_SHIFT;
340+
break;
341+
case 2:
342+
clock_enabled = (SIM->SCGC5 & SIM_SCGC5_LPUART2_MASK) >> SIM_SCGC5_LPUART2_SHIFT;
343+
break;
344+
default:
345+
break;
346+
}
334347

335-
/* Wait till data is flushed out of transmit buffer */
336-
while (!(kLPUART_TransmissionCompleteFlag & LPUART_GetStatusFlags((LPUART_Type *)base)))
337-
{
348+
return clock_enabled;
349+
}
350+
351+
bool serial_check_tx_ongoing()
352+
{
353+
LPUART_Type *base;
354+
int i;
355+
bool uart_tx_ongoing = false;
356+
357+
for (i = 0; i < FSL_FEATURE_SOC_LPUART_COUNT; i++) {
358+
/* First check if UART is enabled */
359+
if (!serial_is_enabled(i)) {
360+
/* UART is not enabled, check the next instance */
361+
continue;
362+
}
363+
364+
base = uart_addrs[i];
365+
366+
/* Check if data is waiting to be written out of transmit buffer */
367+
if (!(kLPUART_TransmissionCompleteFlag & LPUART_GetStatusFlags((LPUART_Type *)base))) {
368+
uart_tx_ongoing = true;
369+
break;
370+
}
338371
}
372+
373+
return uart_tx_ongoing;
339374
}
340375

341376
#endif

‎targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/serial_api.c

Lines changed: 40 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -327,14 +327,49 @@ void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, Pi
327327

328328
#endif
329329

330-
void serial_wait_tx_complete(uint32_t uart_index)
330+
static int serial_is_enabled(uint32_t uart_index)
331331
{
332-
UART_Type *base = uart_addrs[uart_index];
332+
int clock_enabled = 0;
333+
switch (uart_index) {
334+
case 0:
335+
clock_enabled = (SIM->SCGC4 & SIM_SCGC4_UART0_MASK) >> SIM_SCGC4_UART0_SHIFT;
336+
break;
337+
case 1:
338+
clock_enabled = (SIM->SCGC4 & SIM_SCGC4_UART1_MASK) >> SIM_SCGC4_UART1_SHIFT;
339+
break;
340+
case 2:
341+
clock_enabled = (SIM->SCGC4 & SIM_SCGC4_UART2_MASK) >> SIM_SCGC4_UART2_SHIFT;
342+
break;
343+
default:
344+
break;
345+
}
333346

334-
/* Wait till data is flushed out of transmit buffer */
335-
while (!(kUART_TransmissionCompleteFlag & UART_GetStatusFlags((UART_Type *)base)))
336-
{
347+
return clock_enabled;
348+
}
349+
350+
bool serial_check_tx_ongoing()
351+
{
352+
UART_Type *base;
353+
int i;
354+
bool uart_tx_ongoing = false;
355+
356+
for (i = 0; i < FSL_FEATURE_SOC_UART_COUNT; i++) {
357+
/* First check if UART is enabled */
358+
if (!serial_is_enabled(i)) {
359+
/* UART is not enabled, check the next instance */
360+
continue;
361+
}
362+
363+
base = uart_addrs[i];
364+
365+
/* Check if data is waiting to be written out of transmit buffer */
366+
if (!(kUART_TransmissionCompleteFlag & UART_GetStatusFlags((UART_Type *)base))) {
367+
uart_tx_ongoing = true;
368+
break;
369+
}
337370
}
371+
372+
return uart_tx_ongoing;
338373
}
339374

340375
#endif

‎targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW41Z/serial_api.c

Lines changed: 20 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -282,14 +282,29 @@ const PinMap *serial_rts_pinmap()
282282
return PinMap_UART_RTS;
283283
}
284284

285-
void serial_wait_tx_complete(uint32_t uart_index)
285+
bool serial_check_tx_ongoing()
286286
{
287-
LPUART_Type *base = uart_addrs[uart_index];
287+
LPUART_Type *base;
288+
int i;
289+
bool uart_tx_ongoing = false;
290+
int clock_enabled = 0;
288291

289-
/* Wait till data is flushed out of transmit buffer */
290-
while (!(kLPUART_TransmissionCompleteFlag & LPUART_GetStatusFlags((LPUART_Type *)base)))
291-
{
292+
/* First check if UART is enabled */
293+
clock_enabled = (SIM->SCGC5 & SIM_SCGC5_LPUART0_MASK) >> SIM_SCGC5_LPUART0_SHIFT;
294+
295+
if (!clock_enabled) {
296+
/* UART is not enabled return */
297+
return uart_tx_ongoing;
298+
}
299+
300+
base = uart_addrs[i];
301+
302+
/* Check if data is waiting to be written out of transmit buffer */
303+
if (!(kLPUART_TransmissionCompleteFlag & LPUART_GetStatusFlags((LPUART_Type *)base))) {
304+
uart_tx_ongoing = true;
292305
}
306+
307+
return uart_tx_ongoing;
293308
}
294309

295310
#endif

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