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bmcdonnell-ionxbmcdonnell-ionx
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a few grammar corrections
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‎features/nanostack/FEATURE_NANOSTACK/sal-stack-nanostack/source/Service_Libs/mdns/fnet/fnet_stack/services/dns/fnet_dns.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -122,7 +122,7 @@ struct fnet_dns_params
122122
fnet_address_family_t addr_family; /**< @brief Family of the IP Address which is queried.*/
123123
fnet_dns_callback_resolved_t callback; /**< @brief Pointer to the callback function defined by
124124
* @ref fnet_dns_callback_resolved_t. It is called when the
125-
* DNS-client resolving is finished or an error is occurred. */
125+
* DNS-client resolving is finished or an error has occurred. */
126126
fnet_uint32_t cookie; /**< @brief Optional application-specific parameter. @n
127127
* It's passed to the @c callback
128128
* function as input parameter. */
@@ -155,7 +155,7 @@ extern "C" {
155155
* The resolved IP-address will be passed to the @ref fnet_dns_callback_resolved_t callback function,
156156
* which is set in @c params. @n
157157
* The DNS service is released automatically as soon as the
158-
* resolving is finished or an error is occurred.
158+
* resolving is finished or an error has occurred.
159159
*
160160
******************************************************************************/
161161
fnet_return_t fnet_dns_init( struct fnet_dns_params *params );

‎targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_flexcan.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -227,7 +227,7 @@ enum _flexcan_interrupt_enable
227227
*
228228
* This provides constants for the FlexCAN status flags for use in the FlexCAN functions.
229229
* Note: The CPU read action clears FlEXCAN_ErrorFlag, therefore user need to
230-
* read FlEXCAN_ErrorFlag and distinguish which error is occur using
230+
* read FlEXCAN_ErrorFlag and distinguish which error has occurred using
231231
* @ref _flexcan_error_flags enumerations.
232232
*/
233233
enum _flexcan_flags

‎targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_flexcan.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -227,7 +227,7 @@ enum _flexcan_interrupt_enable
227227
*
228228
* This provides constants for the FlexCAN status flags for use in the FlexCAN functions.
229229
* Note: The CPU read action clears FlEXCAN_ErrorFlag, therefore user need to
230-
* read FlEXCAN_ErrorFlag and distinguish which error is occur using
230+
* read FlEXCAN_ErrorFlag and distinguish which error has occurred using
231231
* @ref _flexcan_error_flags enumerations.
232232
*/
233233
enum _flexcan_flags

‎targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/drivers/fsl_flexcan.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -227,7 +227,7 @@ enum _flexcan_interrupt_enable
227227
*
228228
* This provides constants for the FlexCAN status flags for use in the FlexCAN functions.
229229
* Note: The CPU read action clears FlEXCAN_ErrorFlag, therefore user need to
230-
* read FlEXCAN_ErrorFlag and distinguish which error is occur using
230+
* read FlEXCAN_ErrorFlag and distinguish which error has occurred using
231231
* @ref _flexcan_error_flags enumerations.
232232
*/
233233
enum _flexcan_flags

‎targets/TARGET_NUVOTON/TARGET_M480/device/M480.h

Lines changed: 20 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -3469,7 +3469,7 @@ typedef struct {
34693469
* | | |Note2: This bit is write protected. Refer to the SYS_REGLCTL register.
34703470
* |[6] |PDWKIF |Power-down Mode Wake-up Interrupt Status
34713471
* | | |Set by "Power-down wake-up event", it indicates that resume from Power-down mode.
3472-
* | | |The flag is set if any wake-up source is occurred. Refer Power Modes and Wake-up Sources chapter.
3472+
* | | |The flag is set if any wake-up source has occurred. Refer Power Modes and Wake-up Sources chapter.
34733473
* | | |Note1: Write 1 to clear the bit to 0.
34743474
* | | |Note2: This bit works only if PDWKIEN (CLK_PWRCTL[5]) set to 1.
34753475
* |[7] |PDEN |System Power-down Enable (Write Protect)
@@ -25914,7 +25914,7 @@ typedef struct {
2591425914
* | | |0 = DMA Disabled.
2591525915
* | | |1 = DMA Enabled.
2591625916
* | | |If this bit is cleared, DMA will ignore all requests from SD host and force bus master into IDLE state.
25917-
* | | |Note: If target abort is occurred, DMAEN will be cleared.
25917+
* | | |Note: If target abort has occurred, DMAEN will be cleared.
2591825918
* |[1] |DMARST |Software Engine Reset
2591925919
* | | |0 = No effect.
2592025920
* | | |1 = Reset internal state machine and pointers
@@ -26006,7 +26006,7 @@ typedef struct {
2600626006
* | :----: | :----: | :---- |
2600726007
* |[0] |DTAIF |DMA READ/WRITE Target Abort Interrupt Flag (Read Only)
2600826008
* | | |This bit indicates DMA received an ERROR response from internal AHB bus during DMA read/write operation
26009-
* | | |When Target Abort is occurred, please reset all engine.
26009+
* | | |When Target Abort has occurred, please reset all engine.
2601026010
* | | |0 = No bus ERROR response received.
2601126011
* | | |1 = Bus ERROR response received.
2601226012
* | | |Note: This bit is read only, but can be cleared by writing '1' to it.
@@ -26119,12 +26119,12 @@ typedef struct {
2611926119
* | | |Note: This bit is read only, but can be cleared by writing '1' to it.
2612026120
* |[1] |CRCIF |CRC7, CRC16 and CRC Status Error Interrupt Flag (Read Only)
2612126121
* | | |This bit indicates that SD host has occurred CRC error during response in, data-in or data-out (CRC status error) transfer
26122-
* | | |When CRC error is occurred, software should reset SD engine
26122+
* | | |When CRC error has occurred, software should reset SD engine
2612326123
* | | |Some response (ex
2612426124
* | | |R3) doesn't have CRC7 information with it; SD host will still calculate CRC7, get CRC error and set this flag
2612526125
* | | |In this condition, software should ignore CRC error and clears this bit manually.
26126-
* | | |0 = No CRC error is occurred.
26127-
* | | |1 = CRC error is occurred.
26126+
* | | |0 = No CRC error has occurred.
26127+
* | | |1 = CRC error has occurred.
2612826128
* | | |Note: This bit is read only, but can be cleared by writing '1' to it.
2612926129
* |[2] |CRC7 |CRC7 Check Status (Read Only)
2613026130
* | | |SD host will check CRC7 correctness during each response in
@@ -27705,60 +27705,60 @@ typedef struct {
2770527705
* | | |This bit conveys the interrupt status for USB specific events endpoint
2770627706
* | | |When set, USB interrupt status register should be read to determine the cause of the interrupt.
2770727707
* | | |0 = No interrupt event occurred.
27708-
* | | |1 = The related interrupt event is occurred.
27708+
* | | |1 = The related interrupt event has occurred.
2770927709
* |[1] |CEPIF |Control Endpoint Interrupt
2771027710
* | | |This bit conveys the interrupt status for control endpoint
2771127711
* | | |When set, Control-ep's interrupt status register should be read to determine the cause of the interrupt.
2771227712
* | | |0 = No interrupt event occurred.
27713-
* | | |1 = The related interrupt event is occurred.
27713+
* | | |1 = The related interrupt event has occurred.
2771427714
* |[2] |EPAIF |Endpoint a Interrupt
2771527715
* | | |When set, the corresponding Endpoint A's interrupt status register should be read to determine the cause of the interrupt.
2771627716
* | | |0 = No interrupt event occurred.
27717-
* | | |1 = The related interrupt event is occurred.
27717+
* | | |1 = The related interrupt event has occurred.
2771827718
* |[3] |EPBIF |Endpoint B Interrupt
2771927719
* | | |When set, the corresponding Endpoint B's interrupt status register should be read to determine the cause of the interrupt.
2772027720
* | | |0 = No interrupt event occurred.
27721-
* | | |1 = The related interrupt event is occurred.
27721+
* | | |1 = The related interrupt event has occurred.
2772227722
* |[4] |EPCIF |Endpoint C Interrupt
2772327723
* | | |When set, the corresponding Endpoint C's interrupt status register should be read to determine the cause of the interrupt.
2772427724
* | | |0 = No interrupt event occurred.
27725-
* | | |1 = The related interrupt event is occurred.
27725+
* | | |1 = The related interrupt event has occurred.
2772627726
* |[5] |EPDIF |Endpoint D Interrupt
2772727727
* | | |When set, the corresponding Endpoint D's interrupt status register should be read to determine the cause of the interrupt.
2772827728
* | | |0 = No interrupt event occurred.
27729-
* | | |1 = The related interrupt event is occurred.
27729+
* | | |1 = The related interrupt event has occurred.
2773027730
* |[6] |EPEIF |Endpoint E Interrupt
2773127731
* | | |When set, the corresponding Endpoint E's interrupt status register should be read to determine the cause of the interrupt.
2773227732
* | | |0 = No interrupt event occurred.
27733-
* | | |1 = The related interrupt event is occurred.
27733+
* | | |1 = The related interrupt event has occurred.
2773427734
* |[7] |EPFIF |Endpoint F Interrupt
2773527735
* | | |When set, the corresponding Endpoint F's interrupt status register should be read to determine the cause of the interrupt.
2773627736
* | | |0 = No interrupt event occurred.
27737-
* | | |1 = The related interrupt event is occurred.
27737+
* | | |1 = The related interrupt event has occurred.
2773827738
* |[8] |EPGIF |Endpoint G Interrupt
2773927739
* | | |When set, the corresponding Endpoint G's interrupt status register should be read to determine the cause of the interrupt.
2774027740
* | | |0 = No interrupt event occurred.
27741-
* | | |1 = The related interrupt event is occurred.
27741+
* | | |1 = The related interrupt event has occurred.
2774227742
* |[9] |EPHIF |Endpoint H Interrupt
2774327743
* | | |When set, the corresponding Endpoint H's interrupt status register should be read to determine the cause of the interrupt.
2774427744
* | | |0 = No interrupt event occurred.
27745-
* | | |1 = The related interrupt event is occurred.
27745+
* | | |1 = The related interrupt event has occurred.
2774627746
* |[10] |EPIIF |Endpoint I Interrupt
2774727747
* | | |When set, the corresponding Endpoint I's interrupt status register should be read to determine the cause of the interrupt.
2774827748
* | | |0 = No interrupt event occurred.
27749-
* | | |1 = The related interrupt event is occurred.
27749+
* | | |1 = The related interrupt event has occurred.
2775027750
* |[11] |EPJIF |Endpoint J Interrupt
2775127751
* | | |When set, the corresponding Endpoint J's interrupt status register should be read to determine the cause of the interrupt.
2775227752
* | | |0 = No interrupt event occurred.
27753-
* | | |1 = The related interrupt event is occurred.
27753+
* | | |1 = The related interrupt event has occurred.
2775427754
* |[12] |EPKIF |Endpoint K Interrupt
2775527755
* | | |When set, the corresponding Endpoint K's interrupt status register should be read to determine the cause of the interrupt.
2775627756
* | | |0 = No interrupt event occurred.
27757-
* | | |1 = The related interrupt event is occurred.
27757+
* | | |1 = The related interrupt event has occurred.
2775827758
* |[13] |EPLIF |Endpoint L Interrupt
2775927759
* | | |When set, the corresponding Endpoint L's interrupt status register should be read to determine the cause of the interrupt.
2776027760
* | | |0 = No interrupt event occurred.
27761-
* | | |1 = The related interrupt event is occurred.
27761+
* | | |1 = The related interrupt event has occurred.
2776227762
* @var HSUSBD_T::GINTEN
2776327763
* Offset: 0x08 Global Interrupt Enable Register
2776427764
* ---------------------------------------------------------------------------------------------------

‎targets/TARGET_NUVOTON/TARGET_NANO100/device/Nano100Series.h

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -10976,18 +10976,18 @@ typedef struct {
1097610976
* |[0] |BUS_STS |BUS Interrupt Status
1097710977
* | | |The BUS event means there is bus suspense or bus resume in the bus.
1097810978
* | | |This bit is used to indicate that there is one of events in the bus.
10979-
* | | |0 = No BUS event is occurred.
10979+
* | | |0 = No BUS event has occurred.
1098010980
* | | |1 = BUS event occurred; check USB_BUSSTS [3:0] to know which kind of bus event was occurred, cleared by write "1" to USB_INTSTS [0].
1098110981
* |[1] |USB_STS |USB Interrupt Status
1098210982
* | | |The USB event means that there is Setup Token, IN token, OUT ACK, ISO IN, or ISO OUT event in the bus.
1098310983
* | | |This bit is used to indicate that there is one of events in the bus.
10984-
* | | |0 = No USB event is occurred.
10984+
* | | |0 = No USB event has occurred.
1098510985
* | | |1 = USB event occurred, check EPSTS0~7[3:0] in USB_EPSTS [31:8] to know which kind of USB event was occurred, cleared by write "1" to USB_INTSTS [1] or USB_INTSTS[31] or EPEVT0~7.
1098610986
* |[2] |FLD_STS |Floating Interrupt Status
1098710987
* | | |0 = There is not attached event in the USB.
1098810988
* | | |1 = There is attached event in the USB and it is cleared by write "1" to USB_INTSTS [2].
1098910989
* |[3] |WKEUP_STS |Wake-Up Interrupt Status
10990-
* | | |0 = No wake-up event is occurred.
10990+
* | | |0 = No wake-up event has occurred.
1099110991
* | | |1 = Wake-up event occurred, cleared by write 1 to USB_INTSTS [3].
1099210992
* |[16] |EPEVT0 |USB Event Status On EP0
1099310993
* | | |0 = No event occurred in Endpoint 0.

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