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Commit 08733d1

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LMESTMErwan GOURIOU
LMESTM
authored and
Erwan GOURIOU
committed
[STM32F4] Update to cube V1.10.0
CMSIS to V2.4.2 HAL to V1.4.3
1 parent bddce7c commit 08733d1

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‎hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_B96B_F446VE/stm32f446xx.h

Lines changed: 78 additions & 63 deletions
Large diffs are not rendered by default.

‎hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_B96B_F446VE/stm32f4xx.h

Lines changed: 31 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -2,16 +2,16 @@
22
******************************************************************************
33
* @file stm32f4xx.h
44
* @author MCD Application Team
5-
* @version V2.3.2
6-
* @date 26-June-2015
7-
* @brief CMSIS STM32F4xx Device Peripheral Access Layer Header File.
5+
* @version V2.4.2
6+
* @date 13-November-2015
7+
* @brief CMSIS STM32F4xx Device Peripheral Access Layer Header File.
88
*
99
* The file is the unique include file that the application programmer
1010
* is using in the C source code, usually in main.c. This file contains:
1111
* - Configuration section that allows to select:
1212
* - The STM32F4xx device used in the target application
13-
* - To use or not the peripheral’s drivers in application code(i.e.
14-
* code will be based on direct access to peripheral’s registers
13+
* - To use or not the peripheral's drivers in application code(i.e.
14+
* code will be based on direct access to peripheral's registers
1515
* rather than drivers API), this option is controlled by
1616
* "#define USE_HAL_DRIVER"
1717
*
@@ -76,7 +76,9 @@
7676
*/
7777
#if !defined (STM32F405xx) && !defined (STM32F415xx) && !defined (STM32F407xx) && !defined (STM32F417xx) && \
7878
!defined (STM32F427xx) && !defined (STM32F437xx) && !defined (STM32F429xx) && !defined (STM32F439xx) && \
79-
!defined (STM32F401xC) && !defined (STM32F401xE) && !defined (STM32F411xE) && !defined (STM32F446xx)
79+
!defined (STM32F401xC) && !defined (STM32F401xE) && !defined (STM32F410Tx) && !defined (STM32F410Cx) && \
80+
!defined (STM32F410Rx) && !defined (STM32F411xE) && !defined (STM32F446xx) && !defined (STM32F469xx) && \
81+
!defined (STM32F479xx)
8082
/* #define STM32F405xx */ /*!< STM32F405RG, STM32F405VG and STM32F405ZG Devices */
8183
/* #define STM32F415xx */ /*!< STM32F415RG, STM32F415VG and STM32F415ZG Devices */
8284
/* #define STM32F407xx */ /*!< STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG and STM32F407IE Devices */
@@ -89,9 +91,16 @@
8991
STM32F439NI, STM32F439IG and STM32F439II Devices */
9092
/* #define STM32F401xC */ /*!< STM32F401CB, STM32F401CC, STM32F401RB, STM32F401RC, STM32F401VB and STM32F401VC Devices */
9193
/* #define STM32F401xE */ /*!< STM32F401CD, STM32F401RD, STM32F401VD, STM32F401CE, STM32F401RE and STM32F401VE Devices */
92-
/* #define STM32F411xE */ /*!< STM32F411CD, STM32F411RD, STM32F411VD, STM32F411CE, STM32F411RE and STM32F411VE Devices */
93-
#define STM32F446xx /*!< STM32F446MC, STM32F446ME, STM32F446RC, STM32F446RE, STM32F446VC, STM32F446VE, STM32F446ZC,
94-
and STM32F446ZE Devices */
94+
/* #define STM32F410Tx */ /*!< STM32F410T8 and STM32F410TB Devices */
95+
/* #define STM32F410Cx */ /*!< STM32F410C8 and STM32F410CB Devices */
96+
/* #define STM32F410Rx */ /*!< STM32F410R8 and STM32F410RB Devices */
97+
/* #define STM32F411xE */ /*!< STM32F411CC, STM32F411RC, STM32F411VC, STM32F411CE, STM32F411RE and STM32F411VE Devices */
98+
#define STM32F446xx /*!< STM32F446MC, STM32F446ME, STM32F446RC, STM32F446RE, STM32F446VC, STM32F446VE, STM32F446ZC,
99+
and STM32F446ZE Devices */
100+
/* #define STM32F469xx */ /*!< STM32F469AI, STM32F469II, STM32F469BI, STM32F469NI, STM32F469AG, STM32F469IG, STM32F469BG,
101+
STM32F469NG, STM32F469AE, STM32F469IE, STM32F469BE and STM32F469NE Devices */
102+
/* #define STM32F479xx */ /*!< STM32F479AI, STM32F479II, STM32F479BI, STM32F479NI, STM32F479AG, STM32F479IG, STM32F479BG
103+
and STM32F479NG Devices */
95104
#endif
96105

97106
/* Tip: To avoid modifying this file each time you need to switch between these
@@ -107,17 +116,17 @@
107116
#endif /* USE_HAL_DRIVER */
108117

109118
/**
110-
* @brief CMSIS Device version number V2.3.2
119+
* @brief CMSIS Device version number V2.4.2
111120
*/
112121
#define __STM32F4xx_CMSIS_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */
113-
#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
122+
#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB1 (0x04) /*!< [23:16] sub1 version */
114123
#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */
115124
#define __STM32F4xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
116125
#define __STM32F4xx_CMSIS_DEVICE_VERSION ((__STM32F4xx_CMSIS_DEVICE_VERSION_MAIN << 24)\
117126
|(__STM32F4xx_CMSIS_DEVICE_VERSION_SUB1 << 16)\
118127
|(__STM32F4xx_CMSIS_DEVICE_VERSION_SUB2 << 8 )\
119128
|(__STM32F4xx_CMSIS_DEVICE_VERSION))
120-
129+
121130
/**
122131
* @}
123132
*/
@@ -146,10 +155,20 @@
146155
#include "stm32f401xc.h"
147156
#elif defined(STM32F401xE)
148157
#include "stm32f401xe.h"
158+
#elif defined(STM32F410Tx)
159+
#include "stm32f410tx.h"
160+
#elif defined(STM32F410Cx)
161+
#include "stm32f410cx.h"
162+
#elif defined(STM32F410Rx)
163+
#include "stm32f410rx.h"
149164
#elif defined(STM32F411xE)
150165
#include "stm32f411xe.h"
151166
#elif defined(STM32F446xx)
152167
#include "stm32f446xx.h"
168+
#elif defined(STM32F469xx)
169+
#include "stm32f469xx.h"
170+
#elif defined(STM32F479xx)
171+
#include "stm32f479xx.h"
153172
#else
154173
#error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)"
155174
#endif

‎hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_B96B_F446VE/system_stm32f4xx.c

Lines changed: 197 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -2,8 +2,8 @@
22
******************************************************************************
33
* @file system_stm32f4xx.c
44
* @author MCD Application Team
5-
* @version V2.3.2
6-
* @date 26-June-2015
5+
* @version V2.4.2
6+
* @date 13-November-2015
77
* @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
88
*
99
* This file provides two functions and one global variable to be called from
@@ -106,19 +106,17 @@
106106

107107
/************************* Miscellaneous Configuration ************************/
108108
/*!< Uncomment the following line if you need to use external SRAM or SDRAM as data memory */
109-
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
110-
defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
109+
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\
110+
|| defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
111+
|| defined(STM32F469xx) || defined(STM32F479xx)
111112
/* #define DATA_IN_ExtSRAM */
112-
#endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx */
113+
#endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F469xx || STM32F479xx */
113114

114-
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
115-
defined(STM32F446xx)
115+
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
116+
|| defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
116117
/* #define DATA_IN_ExtSDRAM */
117-
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx */
118-
119-
#if defined(DATA_IN_ExtSRAM) && defined(DATA_IN_ExtSDRAM)
120-
#error "Please select DATA_IN_ExtSRAM or DATA_IN_ExtSDRAM "
121-
#endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */
118+
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx ||\
119+
STM32F479xx */
122120

123121
/*!< Uncomment the following line if you need to relocate your vector Table in
124122
Internal SRAM. */
@@ -327,7 +325,9 @@ void SystemCoreClockUpdate(void)
327325
SystemCoreClock >>= tmp;
328326
}
329327

330-
#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
328+
#if defined (DATA_IN_ExtSRAM) && defined (DATA_IN_ExtSDRAM)
329+
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
330+
defined(STM32F469xx) || defined(STM32F479xx)
331331
/**
332332
* @brief Setup the external memory controller.
333333
* Called in startup_stm32f4xx.s before jump to main.
@@ -339,7 +339,171 @@ void SystemCoreClockUpdate(void)
339339
void SystemInit_ExtMemCtl(void)
340340
{
341341
__IO uint32_t tmp = 0x00;
342-
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx)
342+
343+
register uint32_t tmpreg = 0, timeout = 0xFFFF;
344+
register uint32_t index;
345+
346+
/* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface clock */
347+
RCC->AHB1ENR |= 0x000001F8;
348+
349+
/* Delay after an RCC peripheral clock enabling */
350+
tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);
351+
352+
/* Connect PDx pins to FMC Alternate function */
353+
GPIOD->AFR[0] = 0x00CCC0CC;
354+
GPIOD->AFR[1] = 0xCCCCCCCC;
355+
/* Configure PDx pins in Alternate function mode */
356+
GPIOD->MODER = 0xAAAA0A8A;
357+
/* Configure PDx pins speed to 100 MHz */
358+
GPIOD->OSPEEDR = 0xFFFF0FCF;
359+
/* Configure PDx pins Output type to push-pull */
360+
GPIOD->OTYPER = 0x00000000;
361+
/* No pull-up, pull-down for PDx pins */
362+
GPIOD->PUPDR = 0x00000000;
363+
364+
/* Connect PEx pins to FMC Alternate function */
365+
GPIOE->AFR[0] = 0xC00CC0CC;
366+
GPIOE->AFR[1] = 0xCCCCCCCC;
367+
/* Configure PEx pins in Alternate function mode */
368+
GPIOE->MODER = 0xAAAA828A;
369+
/* Configure PEx pins speed to 100 MHz */
370+
GPIOE->OSPEEDR = 0xFFFFC3CF;
371+
/* Configure PEx pins Output type to push-pull */
372+
GPIOE->OTYPER = 0x00000000;
373+
/* No pull-up, pull-down for PEx pins */
374+
GPIOE->PUPDR = 0x00000000;
375+
376+
/* Connect PFx pins to FMC Alternate function */
377+
GPIOF->AFR[0] = 0xCCCCCCCC;
378+
GPIOF->AFR[1] = 0xCCCCCCCC;
379+
/* Configure PFx pins in Alternate function mode */
380+
GPIOF->MODER = 0xAA800AAA;
381+
/* Configure PFx pins speed to 50 MHz */
382+
GPIOF->OSPEEDR = 0xAA800AAA;
383+
/* Configure PFx pins Output type to push-pull */
384+
GPIOF->OTYPER = 0x00000000;
385+
/* No pull-up, pull-down for PFx pins */
386+
GPIOF->PUPDR = 0x00000000;
387+
388+
/* Connect PGx pins to FMC Alternate function */
389+
GPIOG->AFR[0] = 0xCCCCCCCC;
390+
GPIOG->AFR[1] = 0xCCCCCCCC;
391+
/* Configure PGx pins in Alternate function mode */
392+
GPIOG->MODER = 0xAAAAAAAA;
393+
/* Configure PGx pins speed to 50 MHz */
394+
GPIOG->OSPEEDR = 0xAAAAAAAA;
395+
/* Configure PGx pins Output type to push-pull */
396+
GPIOG->OTYPER = 0x00000000;
397+
/* No pull-up, pull-down for PGx pins */
398+
GPIOG->PUPDR = 0x00000000;
399+
400+
/* Connect PHx pins to FMC Alternate function */
401+
GPIOH->AFR[0] = 0x00C0CC00;
402+
GPIOH->AFR[1] = 0xCCCCCCCC;
403+
/* Configure PHx pins in Alternate function mode */
404+
GPIOH->MODER = 0xAAAA08A0;
405+
/* Configure PHx pins speed to 50 MHz */
406+
GPIOH->OSPEEDR = 0xAAAA08A0;
407+
/* Configure PHx pins Output type to push-pull */
408+
GPIOH->OTYPER = 0x00000000;
409+
/* No pull-up, pull-down for PHx pins */
410+
GPIOH->PUPDR = 0x00000000;
411+
412+
/* Connect PIx pins to FMC Alternate function */
413+
GPIOI->AFR[0] = 0xCCCCCCCC;
414+
GPIOI->AFR[1] = 0x00000CC0;
415+
/* Configure PIx pins in Alternate function mode */
416+
GPIOI->MODER = 0x0028AAAA;
417+
/* Configure PIx pins speed to 50 MHz */
418+
GPIOI->OSPEEDR = 0x0028AAAA;
419+
/* Configure PIx pins Output type to push-pull */
420+
GPIOI->OTYPER = 0x00000000;
421+
/* No pull-up, pull-down for PIx pins */
422+
GPIOI->PUPDR = 0x00000000;
423+
424+
/*-- FMC Configuration -------------------------------------------------------*/
425+
/* Enable the FMC interface clock */
426+
RCC->AHB3ENR |= 0x00000001;
427+
/* Delay after an RCC peripheral clock enabling */
428+
tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
429+
430+
FMC_Bank5_6->SDCR[0] = 0x000019E4;
431+
FMC_Bank5_6->SDTR[0] = 0x01115351;
432+
433+
/* SDRAM initialization sequence */
434+
/* Clock enable command */
435+
FMC_Bank5_6->SDCMR = 0x00000011;
436+
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
437+
while((tmpreg != 0) && (timeout-- > 0))
438+
{
439+
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
440+
}
441+
442+
/* Delay */
443+
for (index = 0; index<1000; index++);
444+
445+
/* PALL command */
446+
FMC_Bank5_6->SDCMR = 0x00000012;
447+
timeout = 0xFFFF;
448+
while((tmpreg != 0) && (timeout-- > 0))
449+
{
450+
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
451+
}
452+
453+
/* Auto refresh command */
454+
FMC_Bank5_6->SDCMR = 0x00000073;
455+
timeout = 0xFFFF;
456+
while((tmpreg != 0) && (timeout-- > 0))
457+
{
458+
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
459+
}
460+
461+
/* MRD register program */
462+
FMC_Bank5_6->SDCMR = 0x00046014;
463+
timeout = 0xFFFF;
464+
while((tmpreg != 0) && (timeout-- > 0))
465+
{
466+
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
467+
}
468+
469+
/* Set refresh count */
470+
tmpreg = FMC_Bank5_6->SDRTR;
471+
FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1));
472+
473+
/* Disable write protection */
474+
tmpreg = FMC_Bank5_6->SDCR[0];
475+
FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
476+
477+
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
478+
/* Configure and enable Bank1_SRAM2 */
479+
FMC_Bank1->BTCR[2] = 0x00001011;
480+
FMC_Bank1->BTCR[3] = 0x00000201;
481+
FMC_Bank1E->BWTR[2] = 0x0fffffff;
482+
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
483+
#if defined(STM32F469xx) || defined(STM32F479xx)
484+
/* Configure and enable Bank1_SRAM2 */
485+
FMC_Bank1->BTCR[2] = 0x00001091;
486+
FMC_Bank1->BTCR[3] = 0x00110212;
487+
FMC_Bank1E->BWTR[2] = 0x0fffffff;
488+
#endif /* STM32F469xx || STM32F479xx */
489+
490+
(void)(tmp);
491+
}
492+
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
493+
#elif defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
494+
/**
495+
* @brief Setup the external memory controller.
496+
* Called in startup_stm32f4xx.s before jump to main.
497+
* This function configures the external memories (SRAM/SDRAM)
498+
* This SRAM/SDRAM will be used as program data memory (including heap and stack).
499+
* @param None
500+
* @retval None
501+
*/
502+
void SystemInit_ExtMemCtl(void)
503+
{
504+
__IO uint32_t tmp = 0x00;
505+
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
506+
|| defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
343507
#if defined (DATA_IN_ExtSDRAM)
344508
register uint32_t tmpreg = 0, timeout = 0xFFFF;
345509
register uint32_t index;
@@ -430,7 +594,8 @@ void SystemInit_ExtMemCtl(void)
430594
/* No pull-up, pull-down for PGx pins */
431595
GPIOG->PUPDR = 0x00000000;
432596

433-
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
597+
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
598+
|| defined(STM32F469xx) || defined(STM32F479xx)
434599
/* Connect PHx pins to FMC Alternate function */
435600
GPIOH->AFR[0] = 0x00C0CC00;
436601
GPIOH->AFR[1] = 0xCCCCCCCC;
@@ -454,7 +619,7 @@ void SystemInit_ExtMemCtl(void)
454619
GPIOI->OTYPER = 0x00000000;
455620
/* No pull-up, pull-down for PIx pins */
456621
GPIOI->PUPDR = 0x00000000;
457-
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
622+
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
458623

459624
/*-- FMC Configuration -------------------------------------------------------*/
460625
/* Enable the FMC interface clock */
@@ -526,10 +691,11 @@ void SystemInit_ExtMemCtl(void)
526691
tmpreg = FMC_Bank5_6->SDCR[0];
527692
FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
528693
#endif /* DATA_IN_ExtSDRAM */
529-
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx */
694+
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
530695

531-
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
532-
defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
696+
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\
697+
|| defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
698+
|| defined(STM32F469xx) || defined(STM32F479xx)
533699

534700
#if defined(DATA_IN_ExtSRAM)
535701
/*-- GPIOs Configuration -----------------------------------------------------*/
@@ -590,15 +756,22 @@ void SystemInit_ExtMemCtl(void)
590756
/* Enable the FMC/FSMC interface clock */
591757
RCC->AHB3ENR |= 0x00000001;
592758

593-
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
759+
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
594760
/* Delay after an RCC peripheral clock enabling */
595761
tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
596762
/* Configure and enable Bank1_SRAM2 */
597763
FMC_Bank1->BTCR[2] = 0x00001011;
598764
FMC_Bank1->BTCR[3] = 0x00000201;
599765
FMC_Bank1E->BWTR[2] = 0x0fffffff;
600766
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
601-
767+
#if defined(STM32F469xx) || defined(STM32F479xx)
768+
/* Delay after an RCC peripheral clock enabling */
769+
tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
770+
/* Configure and enable Bank1_SRAM2 */
771+
FMC_Bank1->BTCR[2] = 0x00001091;
772+
FMC_Bank1->BTCR[3] = 0x00110212;
773+
FMC_Bank1E->BWTR[2] = 0x0fffffff;
774+
#endif /* STM32F469xx || STM32F479xx */
602775
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
603776
/* Delay after an RCC peripheral clock enabling */
604777
tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);
@@ -609,10 +782,11 @@ void SystemInit_ExtMemCtl(void)
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#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
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#endif /* DATA_IN_ExtSRAM */
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#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
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#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\
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STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
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(void)(tmp);
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}
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#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
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#endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */
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/**
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* @brief Configures the System clock source, PLL Multiplier and Divider factors,

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