CMSIS/RTX: Pre-processor defines used for assembly

CMSIS repo does not support pre-processor defines, hence multiple assembly
files are added for secure/non-secure and floating point tools.
Mbed OS tools support assembly file pre-processing, but the build system
does not support multiple assembly files for each target, hence updating
the assembly files.

1. Patch RTX so irq_cm4f.S files work with no FPU targets
2. Patch RTX so irq_armv8mml.S files to work with and without FPU
2. Patch RTX so irq_armv8mml.S and irq_armv8mbl.S files to work with secure and
   non-secure builds

Author: bulislaw

rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_ARM/TARGET_M23/irq_armv8mbl.S

@@ -24,9 +24,9 @@
 ; */
 
 
-                IF       :LNOT::DEF:DOMAIN_NS
-DOMAIN_NS       EQU      0
-                ENDIF
+#ifndef DOMAIN_NS
+DOMAIN_NS     EQU      0
+#endif
 
 I_T_RUN_OFS     EQU      20                     ; osRtxInfo.thread.run offset
 TCB_SM_OFS      EQU      48                     ; TCB.stack_mem offset

rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_ARM/TARGET_M33/irq_armv8mml.S

@@ -24,15 +24,16 @@
 ; */
 
 
-                IF       :LNOT::DEF:DOMAIN_NS
-DOMAIN_NS       EQU      0
-                ENDIF
+#ifndef DOMAIN_NS
+DOMAIN_NS     EQU      0
+#endif
 
-                IF       ({FPU}="FPv5-SP") || ({FPU}="FPv5_D16")
+#ifdef __ARM_FP
 __FPU_USED      EQU      1
-                ELSE
+#else
 __FPU_USED      EQU      0
-                ENDIF
+#endif
+
 
 I_T_RUN_OFS     EQU      20                     ; osRtxInfo.thread.run offset
 TCB_SM_OFS      EQU      48                     ; TCB.stack_mem offset

rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_ARM/TARGET_RTOS_M4_M7/irq_cm4f.S

@@ -74,17 +74,22 @@ SVC_Context
                 CBNZ     R1,SVC_ContextSave     ; Branch if running thread is not deleted
                 TST      LR,#0x10               ; Check if extended stack frame
                 BNE      SVC_ContextSwitch
+#ifdef __FPU_PRESENT
                 LDR      R1,=0xE000EF34         ; FPCCR Address
                 LDR      R0,[R1]                ; Load FPCCR
                 BIC      R0,R0,#1               ; Clear LSPACT (Lazy state)
                 STR      R0,[R1]                ; Store FPCCR
                 B        SVC_ContextSwitch
+#endif
 
 SVC_ContextSave
                 STMDB    R12!,{R4-R11}          ; Save R4..R11
+#ifdef __FPU_PRESENT
                 TST      LR,#0x10               ; Check if extended stack frame
                 IT       EQ
                 VSTMDBEQ R12!,{S16-S31}         ;  Save VFP S16.S31
+#endif
+
                 STR      R12,[R1,#TCB_SP_OFS]   ; Store SP
                 STRB     LR, [R1,#TCB_SF_OFS]   ; Store stack frame information
 
@@ -103,9 +108,11 @@ SVC_ContextRestore
                 LDR      R0,[R2,#TCB_SP_OFS]    ; Load SP
                 ORR      LR,R1,#0xFFFFFF00      ; Set EXC_RETURN
 
+#ifdef __FPU_PRESENT
                 TST      LR,#0x10               ; Check if extended stack frame
                 IT       EQ
                 VLDMIAEQ R0!,{S16-S31}          ;  Restore VFP S16..S31
+#endif
                 LDMIA    R0!,{R4-R11}           ; Restore R4..R11
                 MSR      PSP,R0                 ; Set PSP
 

rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_GCC/TARGET_M23/irq_armv8mbl.S

@@ -27,9 +27,9 @@
         .file    "irq_armv8mbl.S"
         .syntax  unified
 
-        .ifndef  DOMAIN_NS
+#ifndef  DOMAIN_NS
         .equ     DOMAIN_NS, 0
-        .endif
+#endif
 
         .equ     I_T_RUN_OFS, 20        // osRtxInfo.thread.run offset
         .equ     TCB_SM_OFS,  48        // TCB.stack_mem offset

rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_GCC/TARGET_M33/irq_armv8mml.S

@@ -27,13 +27,15 @@
         .file    "irq_armv8mml.S"
         .syntax  unified
 
-        .ifndef  DOMAIN_NS
+#ifndef DOMAIN_NS
         .equ     DOMAIN_NS, 0
-        .endif
+#endif
 
-        .ifndef  __FPU_USED
+#if defined (__VFP_FP__) && !defined(__SOFTFP__)
+        .equ     __FPU_USED,  1
+#else
         .equ     __FPU_USED,  0
-        .endif
+#endif
 
         .equ     I_T_RUN_OFS, 20        // osRtxInfo.thread.run offset
         .equ     TCB_SM_OFS,  48        // TCB.stack_mem offset

rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_GCC/TARGET_RTOS_M4_M7/irq_cm4f.S

@@ -74,17 +74,22 @@ SVC_Context:
         CBNZ     R1,SVC_ContextSave     // Branch if running thread is not deleted
         TST      LR,#0x10               // Check if extended stack frame
         BNE      SVC_ContextSwitch
+#ifdef __FPU_PRESENT
         LDR      R1,=0xE000EF34         // FPCCR Address
         LDR      R0,[R1]                // Load FPCCR
         BIC      R0,R0,#1               // Clear LSPACT (Lazy state)
         STR      R0,[R1]                // Store FPCCR
         B        SVC_ContextSwitch
+#endif
 
 SVC_ContextSave:
         STMDB    R12!,{R4-R11}          // Save R4..R11
+#ifdef __FPU_PRESENT
         TST      LR,#0x10               // Check if extended stack frame
         IT       EQ
         VSTMDBEQ R12!,{S16-S31}         //  Save VFP S16.S31
+#endif
+
         STR      R12,[R1,#TCB_SP_OFS]   // Store SP
         STRB     LR, [R1,#TCB_SF_OFS]   // Store stack frame information
 
@@ -96,9 +101,11 @@ SVC_ContextRestore:
         LDR      R0,[R2,#TCB_SP_OFS]    // Load SP
         ORR      LR,R1,#0xFFFFFF00      // Set EXC_RETURN
 
+#ifdef __FPU_PRESENT
         TST      LR,#0x10               // Check if extended stack frame
         IT       EQ
         VLDMIAEQ R0!,{S16-S31}          //  Restore VFP S16..S31
+#endif
         LDMIA    R0!,{R4-R11}           // Restore R4..R11
         MSR      PSP,R0                 // Set PSP
 

rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_IAR/TARGET_M23/irq_armv8mbl_common.S

@@ -297,3 +297,5 @@ Sys_ContextRestore2
 
 Sys_ContextExit
                 BX       LR                     ; Exit from handler
+
+                END

rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_IAR/TARGET_M33/irq_armv8mml_common.S

@@ -270,3 +270,5 @@ Sys_ContextRestore2
 
 Sys_ContextExit
                 BX       LR                     ; Exit from handler
+
+                END

rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_IAR/TARGET_RTOS_M4_M7/irq_cm4f.S

@@ -74,17 +74,22 @@ SVC_Context
                 CBNZ     R1,SVC_ContextSave     ; Branch if running thread is not deleted
                 TST      LR,#0x10               ; Check if extended stack frame
                 BNE      SVC_ContextSwitch
+#ifdef __FPU_PRESENT
                 LDR      R1,=0xE000EF34         ; FPCCR Address
                 LDR      R0,[R1]                ; Load FPCCR
                 BIC      R0,R0,#1               ; Clear LSPACT (Lazy state)
                 STR      R0,[R1]                ; Store FPCCR
                 B        SVC_ContextSwitch
+#endif
 
 SVC_ContextSave
                 STMDB    R12!,{R4-R11}          ; Save R4..R11
+#ifdef __FPU_PRESENT
                 TST      LR,#0x10               ; Check if extended stack frame
                 IT       EQ
                 VSTMDBEQ R12!,{S16-S31}         ;  Save VFP S16.S31
+#endif
+
                 STR      R12,[R1,#TCB_SP_OFS]   ; Store SP
                 STRB     LR, [R1,#TCB_SF_OFS]   ; Store stack frame information
 
@@ -96,9 +101,11 @@ SVC_ContextRestore
                 LDR      R0,[R2,#TCB_SP_OFS]    ; Load SP
                 ORR      LR,R1,#0xFFFFFF00      ; Set EXC_RETURN
 
+#ifdef __FPU_PRESENT
                 TST      LR,#0x10               ; Check if extended stack frame
                 IT       EQ
                 VLDMIAEQ R0!,{S16-S31}          ;  Restore VFP S16..S31
+#endif
                 LDMIA    R0!,{R4-R11}           ; Restore R4..R11
                 MSR      PSP,R0                 ; Set PSP