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Cruz Monrreal
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Merge pull request #8485 from NXPmicro/feature-qspi-kinetis
Feature qspi kinetis
2 parents cd55994 + 86ae041 commit 0db8960

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‎TESTS/mbed_hal/qspi/flash_configs/Freescale/K82F/flash_config.h

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/* mbed Microcontroller Library
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* Copyright (c) 2018-2018 ARM Limited
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef MBED_QSPI_FLASH_CONFIG_H
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#define MBED_QSPI_FLASH_CONFIG_H
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#include "../../MX25RXX35F_config.h"
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/* Fast mode not supported in MX25U3235F */
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#undef FAST_MODE_ENABLE
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#undef FAST_MODE_DISABLE
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#ifdef QSPI_SECTOR_COUNT
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#undef QSPI_SECTOR_COUNT
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#define QSPI_SECTOR_COUNT 1024 // for MX25U3235F
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#endif
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/* The values for MX25U3235F are different, specify this here */
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#undef QSPI_COMMON_MAX_FREQUENCY
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#undef QSPI_WRSR_MAX_TIME
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#undef QSPI_PAGE_PROG_MAX_TIME
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#undef QSPI_ERASE_SECTOR_MAX_TIME
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#undef QSPI_ERASE_BLOCK_32_MAX_TIME
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#undef QSPI_ERASE_BLOCK_64_MAX_TIME
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/* Implementation of these macros are slightly different for MX25U3235F */
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#undef EXTENDED_SPI_ENABLE
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#undef EXTENDED_SPI_DISABLE
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/* Max frequency for basic rw operation in MX25U3235F */
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#define QSPI_COMMON_MAX_FREQUENCY 54000000
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/* WRSR operations max time [us] (datasheet max time + 15%) */
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#define QSPI_WRSR_MAX_TIME 46000 // 40ms
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/* Write operations max time [us] (datasheet max time + 15%) */
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#define QSPI_PAGE_PROG_MAX_TIME 3450 // 3ms
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/* erase operations max time [us] (datasheet max time + 15%) */
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#define QSPI_ERASE_SECTOR_MAX_TIME 230000 // 200 ms
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#define QSPI_ERASE_BLOCK_32_MAX_TIME 1150000 // 1s
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#define QSPI_ERASE_BLOCK_64_MAX_TIME 2300000 // 2s
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#define EXTENDED_SPI_ENABLE() \
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\
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const int32_t reg_size = QSPI_STATUS_REG_SIZE; \
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uint8_t reg_data[reg_size] = { 0 }; \
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\
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if (read_register(STATUS_REG, reg_data, \
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QSPI_STATUS_REG_SIZE, qspi) != QSPI_STATUS_OK) { \
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return QSPI_STATUS_ERROR; \
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} \
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if (write_enable(qspi) != QSPI_STATUS_OK) { \
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return QSPI_STATUS_ERROR; \
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} \
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\
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reg_data[0] = STATUS_BIT_QE; \
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if (write_register(QSPI_CMD_WRSR, reg_data, \
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reg_size, qspi) != QSPI_STATUS_OK) { \
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return QSPI_STATUS_ERROR; \
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} \
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WAIT_FOR(WRSR_MAX_TIME, qspi); \
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\
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memset(reg_data, 0, QSPI_STATUS_REG_SIZE); \
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if (read_register(STATUS_REG, reg_data, \
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QSPI_STATUS_REG_SIZE, qspi) != QSPI_STATUS_OK) { \
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return QSPI_STATUS_ERROR; \
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} \
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\
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return ((reg_data[0] & STATUS_BIT_QE) != 0 ? \
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QSPI_STATUS_OK : QSPI_STATUS_ERROR)
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#define EXTENDED_SPI_DISABLE() \
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\
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const int32_t reg_size = QSPI_STATUS_REG_SIZE; \
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uint8_t reg_data[reg_size] = { 0 }; \
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\
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if (read_register(STATUS_REG, reg_data, \
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QSPI_STATUS_REG_SIZE, qspi) != QSPI_STATUS_OK) { \
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return QSPI_STATUS_ERROR; \
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} \
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\
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if (write_enable(qspi) != QSPI_STATUS_OK) { \
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return QSPI_STATUS_ERROR; \
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} \
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\
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reg_data[0] &= ~(STATUS_BIT_QE); \
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\
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if (write_register(QSPI_CMD_WRSR, reg_data, \
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reg_size, qspi) != QSPI_STATUS_OK) { \
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return QSPI_STATUS_ERROR; \
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} \
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WAIT_FOR(WRSR_MAX_TIME, qspi); \
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\
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reg_data[0] = 0; \
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if (read_register(STATUS_REG, reg_data, \
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QSPI_STATUS_REG_SIZE, qspi) != QSPI_STATUS_OK) { \
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return QSPI_STATUS_ERROR; \
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} \
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\
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return ((reg_data[0] & STATUS_BIT_QE) == 0 ? \
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QSPI_STATUS_OK : QSPI_STATUS_ERROR)
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#endif // MBED_QSPI_FLASH_CONFIG_H

‎TESTS/mbed_hal/qspi/flash_configs/Freescale/KL82Z/flash_config.h

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/* mbed Microcontroller Library
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* Copyright (c) 2018-2018 ARM Limited
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13+
* See the License for the specific language governing permissions and
14+
* limitations under the License.
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*/
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#ifndef MBED_QSPI_FLASH_CONFIG_H
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#define MBED_QSPI_FLASH_CONFIG_H
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#include "../../MX25RXX35F_config.h"
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/* Fast mode not supported in MX25L12845G */
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#undef FAST_MODE_ENABLE
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#undef FAST_MODE_DISABLE
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#ifdef QSPI_SECTOR_COUNT
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#undef QSPI_SECTOR_COUNT
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#define QSPI_SECTOR_COUNT 4096 // for MX25L12845G
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#endif
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/* The values for MX25U3235F are different, specify this here */
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#undef QSPI_COMMON_MAX_FREQUENCY
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#undef QSPI_WRSR_MAX_TIME
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#undef QSPI_PAGE_PROG_MAX_TIME
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#undef QSPI_ERASE_SECTOR_MAX_TIME
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#undef QSPI_ERASE_BLOCK_32_MAX_TIME
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#undef QSPI_ERASE_BLOCK_64_MAX_TIME
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/* Implementation of these macros are slightly different for MX25L12845G */
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#undef EXTENDED_SPI_ENABLE
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#undef EXTENDED_SPI_DISABLE
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/* Max frequency for basic rw operation based on max bus frequency of 24MHz */
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#define QSPI_COMMON_MAX_FREQUENCY 23000000
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/* WRSR operations max time [us] (datasheet max time + 15%) */
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#define QSPI_WRSR_MAX_TIME 46000 // 40ms
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/* Write operations max time [us] (datasheet max time + 15%) */
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#define QSPI_PAGE_PROG_MAX_TIME 1000 // 0.75ms
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/* erase operations max time [us] (datasheet max time + 15%) */
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#define QSPI_ERASE_SECTOR_MAX_TIME 460000 // 400 ms
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#define QSPI_ERASE_BLOCK_32_MAX_TIME 1150000 // 1s
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#define QSPI_ERASE_BLOCK_64_MAX_TIME 2300000 // 2s
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#define EXTENDED_SPI_ENABLE() \
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\
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const int32_t reg_size = QSPI_STATUS_REG_SIZE; \
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uint8_t reg_data[reg_size] = { 0 }; \
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\
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if (read_register(STATUS_REG, reg_data, \
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QSPI_STATUS_REG_SIZE, qspi) != QSPI_STATUS_OK) { \
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return QSPI_STATUS_ERROR; \
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} \
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if (write_enable(qspi) != QSPI_STATUS_OK) { \
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return QSPI_STATUS_ERROR; \
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} \
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\
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reg_data[0] = STATUS_BIT_QE; \
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if (write_register(QSPI_CMD_WRSR, reg_data, \
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reg_size, qspi) != QSPI_STATUS_OK) { \
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return QSPI_STATUS_ERROR; \
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} \
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WAIT_FOR(WRSR_MAX_TIME, qspi); \
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\
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memset(reg_data, 0, QSPI_STATUS_REG_SIZE); \
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if (read_register(STATUS_REG, reg_data, \
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QSPI_STATUS_REG_SIZE, qspi) != QSPI_STATUS_OK) { \
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return QSPI_STATUS_ERROR; \
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} \
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\
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return ((reg_data[0] & STATUS_BIT_QE) != 0 ? \
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QSPI_STATUS_OK : QSPI_STATUS_ERROR)
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#define EXTENDED_SPI_DISABLE() \
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\
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const int32_t reg_size = QSPI_STATUS_REG_SIZE; \
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uint8_t reg_data[reg_size] = { 0 }; \
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\
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if (read_register(STATUS_REG, reg_data, \
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QSPI_STATUS_REG_SIZE, qspi) != QSPI_STATUS_OK) { \
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return QSPI_STATUS_ERROR; \
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} \
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\
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if (write_enable(qspi) != QSPI_STATUS_OK) { \
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return QSPI_STATUS_ERROR; \
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} \
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\
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reg_data[0] &= ~(STATUS_BIT_QE); \
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\
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if (write_register(QSPI_CMD_WRSR, reg_data, \
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reg_size, qspi) != QSPI_STATUS_OK) { \
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return QSPI_STATUS_ERROR; \
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} \
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WAIT_FOR(WRSR_MAX_TIME, qspi); \
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\
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reg_data[0] = 0; \
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if (read_register(STATUS_REG, reg_data, \
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QSPI_STATUS_REG_SIZE, qspi) != QSPI_STATUS_OK) { \
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return QSPI_STATUS_ERROR; \
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} \
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\
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return ((reg_data[0] & STATUS_BIT_QE) == 0 ? \
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QSPI_STATUS_OK : QSPI_STATUS_ERROR)
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#endif // MBED_QSPI_FLASH_CONFIG_H

‎TESTS/mbed_hal/qspi/flash_configs/flash_configs.h

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@@ -25,6 +25,10 @@
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#include "STM/DISCO_F413ZH/flash_config.h"
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#elif defined(TARGET_EFM32GG11_STK3701)
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#include "SiliconLabs/EFM32GG11_STK3701/flash_config.h"
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#elif defined(TARGET_K82F)
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#include "Freescale/K82F/flash_config.h"
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#elif defined(TARGET_KL82Z)
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#include "Freescale/KL82Z/flash_config.h"
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#endif
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#endif // MBED_FLASH_CONFIGS_H

‎targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/TARGET_FRDM/PeripheralNames.h

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@@ -106,6 +106,10 @@ typedef enum {
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SPI_2 = 2,
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} SPIName;
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typedef enum {
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QSPI_0 = 0
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} QSPIName;
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#ifdef __cplusplus
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}
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#endif

‎targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/TARGET_FRDM/PeripheralPins.c

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@@ -265,3 +265,29 @@ const PinMap PinMap_PWM[] = {
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266266
{NC , NC , 0}
267267
};
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const PinMap PinMap_QSPI_DATA[] = {
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{PTE0, QSPI_0, 5},
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{PTE2, QSPI_0, 5},
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{PTE3, QSPI_0, 5},
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{PTE4, QSPI_0, 5},
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{PTE6, QSPI_0, 5},
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{PTE7, QSPI_0, 5},
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{PTE8, QSPI_0, 5},
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{PTE9, QSPI_0, 5},
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{PTE10, QSPI_0, 5},
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{NC , NC , 0}
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};
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const PinMap PinMap_QSPI_SCLK[] = {
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{PTE1, QSPI_0, 5},
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{PTE7, QSPI_0, 5},
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{NC , NC , 0}
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};
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const PinMap PinMap_QSPI_SSEL[] = {
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{PTE5, QSPI_0, 5},
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{PTE11, QSPI_0, 5},
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{NC , NC , 0}
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};
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‎targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/TARGET_FRDM/PinNames.h

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@@ -178,6 +178,14 @@ typedef enum {
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SPI_SCK = PTE1,
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SPI_PERSISTENT_MEM_CS = PTE5,
180180

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/**** QSPI FLASH pins ****/
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QSPI_FLASH1_IO0 = PTE2,
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QSPI_FLASH1_IO1 = PTE4,
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QSPI_FLASH1_IO2 = PTE3,
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QSPI_FLASH1_IO3 = PTE0,
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QSPI_FLASH1_SCK = PTE1,
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QSPI_FLASH1_CSN = PTE5,
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// Not connected
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NC = (int)0xFFFFFFFF
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} PinName;

‎targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/TARGET_FRDM/device.h

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@@ -18,22 +18,9 @@
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#ifndef MBED_DEVICE_H
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#define MBED_DEVICE_H
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#include "objects.h"
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#define DEVICE_ID_LENGTH 24
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#define DEVICE_ID_LENGTH 24
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#include "objects.h"
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#endif

‎targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/TARGET_FRDM/mbed_overrides.c

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@@ -62,3 +62,9 @@ void serial_clock_init(void)
6262
CLOCK_SetLpuartClock(2U);
6363
}
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// Get the QSPI clock frequency
66+
uint32_t qspi_get_freq(void)
67+
{
68+
return CLOCK_GetFreq(kCLOCK_McgPll0Clk);
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}
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