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Seppo Takalo
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Merge pull request #11080 from kyle-cypress/pr/cy8ckit-062s2-43012
Add target for CY8CKIT_062S2_43012
2 parents 0d6a3be + 40557ce commit 0e33dd7

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‎features/lwipstack/mbed_lib.json

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"pbuf-pool-size": 48,
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"mem-size": 65536
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},
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"CY8CKIT_062S2_43012": {
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"tcpip-thread-stacksize": 8192,
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"default-thread-stacksize": 640,
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"ppp-thread-stacksize": 896,
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"memp-num-tcp-seg": 24,
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"tcp-socket-max": 10,
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"udp-socket-max":10,
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"socket-max":18,
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"tcp-mss": 1540,
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"tcp-snd-buf": "(6 * TCP_MSS)",
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"tcp-wnd": "(TCP_MSS * 6)",
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"pbuf-pool-size": 96,
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"mem-size": 92610
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},
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"MIMXRT1050_EVK": {
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"mem-size": 36560
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},

‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/GeneratedSource/cycfg.c

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/*******************************************************************************
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* File Name: cycfg.c
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*
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* Description:
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* Wrapper function to initialize all generated code.
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* This file was automatically generated and should not be modified.
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*
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********************************************************************************
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* Copyright 2017-2019 Cypress Semiconductor Corporation
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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********************************************************************************/
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#include "cycfg.h"
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void init_cycfg_all(void)
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{
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init_cycfg_system();
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init_cycfg_clocks();
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init_cycfg_routing();
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init_cycfg_peripherals();
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init_cycfg_pins();
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}

‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/GeneratedSource/cycfg.h

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/*******************************************************************************
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* File Name: cycfg.h
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*
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* Description:
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* Simple wrapper header containing all generated files.
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* This file was automatically generated and should not be modified.
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*
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********************************************************************************
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* Copyright 2017-2019 Cypress Semiconductor Corporation
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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********************************************************************************/
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#if !defined(CYCFG_H)
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#define CYCFG_H
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#if defined(__cplusplus)
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extern "C" {
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#endif
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#include "cycfg_notices.h"
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#include "cycfg_system.h"
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#include "cycfg_clocks.h"
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#include "cycfg_routing.h"
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#include "cycfg_peripherals.h"
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#include "cycfg_pins.h"
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void init_cycfg_all(void);
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#if defined(__cplusplus)
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}
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#endif
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#endif /* CYCFG_H */

‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/GeneratedSource/cycfg_clocks.c

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/*******************************************************************************
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* File Name: cycfg_clocks.c
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*
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* Description:
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* Clock configuration
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* This file was automatically generated and should not be modified.
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*
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********************************************************************************
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* Copyright 2017-2019 Cypress Semiconductor Corporation
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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********************************************************************************/
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#include "cycfg_clocks.h"
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void init_cycfg_clocks(void)
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{
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Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_16_BIT, 0U);
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Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_16_BIT, 0U, 51U);
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Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_16_BIT, 0U);
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Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_16_BIT, 1U);
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Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_16_BIT, 1U, 77U);
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Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_16_BIT, 1U);
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Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 0U);
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Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 0U, 0U);
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Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 0U);
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Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 1U);
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Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 1U, 5U);
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Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 1U);
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}

‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/GeneratedSource/cycfg_clocks.h

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/*******************************************************************************
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* File Name: cycfg_clocks.h
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*
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* Description:
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* Clock configuration
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* This file was automatically generated and should not be modified.
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*
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********************************************************************************
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* Copyright 2017-2019 Cypress Semiconductor Corporation
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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********************************************************************************/
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#if !defined(CYCFG_CLOCKS_H)
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#define CYCFG_CLOCKS_H
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#include "cycfg_notices.h"
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#include "cy_sysclk.h"
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#if defined(__cplusplus)
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extern "C" {
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#endif
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#define CYBSP_DEBUG_UART_CLK_DIV_ENABLED 1U
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#define CYBSP_DEBUG_UART_CLK_DIV_HW CY_SYSCLK_DIV_16_BIT
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#define CYBSP_DEBUG_UART_CLK_DIV_NUM 0U
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#define CYBSP_BT_UART_CLK_DIV_ENABLED 1U
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#define CYBSP_BT_UART_CLK_DIV_HW CY_SYSCLK_DIV_16_BIT
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#define CYBSP_BT_UART_CLK_DIV_NUM 1U
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#define CYBSP_CSD_CLK_DIV_ENABLED 1U
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#define CYBSP_CSD_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
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#define CYBSP_CSD_CLK_DIV_NUM 0U
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#define CYBSP_CSD_COMM_CLK_DIV_ENABLED 1U
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#define CYBSP_CSD_COMM_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
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#define CYBSP_CSD_COMM_CLK_DIV_NUM 1U
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void init_cycfg_clocks(void);
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#if defined(__cplusplus)
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}
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#endif
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#endif /* CYCFG_CLOCKS_H */

‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/GeneratedSource/cycfg_notices.h

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/*******************************************************************************
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* File Name: cycfg_notices.h
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*
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* Description:
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* Contains warnings and errors that occurred while generating code for the
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* design.
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* This file was automatically generated and should not be modified.
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*
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********************************************************************************
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* Copyright 2017-2019 Cypress Semiconductor Corporation
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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********************************************************************************/
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#if !defined(CYCFG_NOTICES_H)
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#define CYCFG_NOTICES_H
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#endif /* CYCFG_NOTICES_H */

‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/GeneratedSource/cycfg_peripherals.c

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/*******************************************************************************
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* File Name: cycfg_peripherals.c
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*
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* Description:
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* Peripheral Hardware Block configuration
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* This file was automatically generated and should not be modified.
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*
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********************************************************************************
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* Copyright 2017-2019 Cypress Semiconductor Corporation
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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********************************************************************************/
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#include "cycfg_peripherals.h"
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cy_stc_csd_context_t cy_csd_0_context =
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{
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.lockKey = CY_CSD_NONE_KEY,
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};
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const cy_stc_scb_uart_config_t CYBSP_BT_UART_config =
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{
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.uartMode = CY_SCB_UART_STANDARD,
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.enableMutliProcessorMode = false,
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.smartCardRetryOnNack = false,
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.irdaInvertRx = false,
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.irdaEnableLowPowerReceiver = false,
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.oversample = 8,
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.enableMsbFirst = false,
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.dataWidth = 8UL,
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.parity = CY_SCB_UART_PARITY_NONE,
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.stopBits = CY_SCB_UART_STOP_BITS_1,
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.enableInputFilter = false,
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.breakWidth = 11UL,
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.dropOnFrameError = false,
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.dropOnParityError = false,
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.receiverAddress = 0x0UL,
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.receiverAddressMask = 0x0UL,
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.acceptAddrInFifo = false,
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.enableCts = true,
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.ctsPolarity = CY_SCB_UART_ACTIVE_LOW,
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.rtsRxFifoLevel = 63,
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.rtsPolarity = CY_SCB_UART_ACTIVE_LOW,
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.rxFifoTriggerLevel = 1UL,
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.rxFifoIntEnableMask = 0UL,
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.txFifoTriggerLevel = 63UL,
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.txFifoIntEnableMask = 0UL,
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};
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const cy_stc_scb_ezi2c_config_t CYBSP_CSD_COMM_config =
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{
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.numberOfAddresses = CY_SCB_EZI2C_ONE_ADDRESS,
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.slaveAddress1 = 8U,
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.slaveAddress2 = 0U,
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.subAddressSize = CY_SCB_EZI2C_SUB_ADDR16_BITS,
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.enableWakeFromSleep = false,
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};
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const cy_stc_scb_uart_config_t CYBSP_DEBUG_UART_config =
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{
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.uartMode = CY_SCB_UART_STANDARD,
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.enableMutliProcessorMode = false,
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.smartCardRetryOnNack = false,
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.irdaInvertRx = false,
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.irdaEnableLowPowerReceiver = false,
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.oversample = 12,
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.enableMsbFirst = false,
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.dataWidth = 9UL,
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.parity = CY_SCB_UART_PARITY_NONE,
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.stopBits = CY_SCB_UART_STOP_BITS_1,
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.enableInputFilter = false,
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.breakWidth = 11UL,
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.dropOnFrameError = false,
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.dropOnParityError = false,
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.receiverAddress = 0x0UL,
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.receiverAddressMask = 0x0UL,
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.acceptAddrInFifo = false,
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.enableCts = true,
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.ctsPolarity = CY_SCB_UART_ACTIVE_HIGH,
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.rtsRxFifoLevel = 63,
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.rtsPolarity = CY_SCB_UART_ACTIVE_LOW,
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.rxFifoTriggerLevel = 63UL,
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.rxFifoIntEnableMask = 0UL,
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.txFifoTriggerLevel = 63UL,
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.txFifoIntEnableMask = 0UL,
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};
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cy_en_sd_host_card_capacity_t CYBSP_RADIO_cardCapacity = CY_SD_HOST_SDSC;
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cy_en_sd_host_card_type_t CYBSP_RADIO_cardType = CY_SD_HOST_NOT_EMMC;
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uint32_t CYBSP_RADIO_rca = 0u;
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const cy_stc_sd_host_init_config_t CYBSP_RADIO_config =
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{
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.emmc = false,
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.dmaType = CY_SD_HOST_DMA_SDMA,
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.enableLedControl = false,
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};
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cy_stc_sd_host_sd_card_config_t CYBSP_RADIO_card_cfg =
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{
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.lowVoltageSignaling = false,
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.busWidth = CY_SD_HOST_BUS_WIDTH_4_BIT,
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.cardType = &CYBSP_RADIO_cardType,
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.rca = &CYBSP_RADIO_rca,
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.cardCapacity = &CYBSP_RADIO_cardCapacity,
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};
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const cy_stc_smif_config_t CYBSP_QSPI_config =
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{
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.mode = (uint32_t)CY_SMIF_NORMAL,
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.deselectDelay = CYBSP_QSPI_DESELECT_DELAY,
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.rxClockSel = (uint32_t)CY_SMIF_SEL_INV_INTERNAL_CLK,
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.blockEvent = (uint32_t)CY_SMIF_BUS_ERROR,
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};
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const cy_stc_mcwdt_config_t CYBSP_MCWDT_config =
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{
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.c0Match = 32768U,
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.c1Match = 32768U,
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.c0Mode = CY_MCWDT_MODE_NONE,
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.c1Mode = CY_MCWDT_MODE_NONE,
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.c2ToggleBit = 16U,
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.c2Mode = CY_MCWDT_MODE_NONE,
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.c0ClearOnMatch = false,
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.c1ClearOnMatch = false,
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.c0c1Cascade = true,
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.c1c2Cascade = false,
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};
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const cy_stc_rtc_config_t CYBSP_RTC_config =
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{
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.sec = 0U,
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.min = 0U,
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.hour = 12U,
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.amPm = CY_RTC_AM,
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.hrFormat = CY_RTC_24_HOURS,
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.dayOfWeek = CY_RTC_SUNDAY,
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.date = 1U,
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.month = CY_RTC_JANUARY,
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.year = 0U,
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};
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void init_cycfg_peripherals(void)
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{
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Cy_SysClk_PeriphAssignDivider(PCLK_CSD_CLOCK, CY_SYSCLK_DIV_8_BIT, 0U);
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Cy_SysClk_PeriphAssignDivider(PCLK_SCB2_CLOCK, CY_SYSCLK_DIV_16_BIT, 1U);
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Cy_SysClk_PeriphAssignDivider(PCLK_SCB3_CLOCK, CY_SYSCLK_DIV_8_BIT, 1U);
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Cy_SysClk_PeriphAssignDivider(PCLK_SCB5_CLOCK, CY_SYSCLK_DIV_16_BIT, 0U);
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}

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