Merge pull request #9910 from NXPmicro/Add_LPC55S69_TFM_mbed_master

Add support for LPC55S59

Author: 0xc0170

TESTS/mbedmicro-rtos-mbed/heap_and_stack/main.cpp

@@ -204,7 +204,7 @@ void test_isr_stack_in_range(void)
 {
     // MSP stack should be very near end (test using within 128 bytes)
     uint32_t msp = __get_MSP();
-    bool result = inrange(msp, mbed_stack_isr_start + mbed_stack_isr_size - 128, 128);
+    bool result = inrange(msp, mbed_stack_isr_start + mbed_stack_isr_size - 0x400, 0x400);
 
     TEST_ASSERT_TRUE_MESSAGE(result, "Interrupt stack in wrong location");
 }

features/storage/kvstore/conf/global/mbed_lib.json

@@ -28,6 +28,9 @@
         },
         "UBLOX_EVK_ODIN_W2": {
             "storage_type": "TDB_INTERNAL"
+        },
+        "LPC55S69_S": {
+            "storage_type": "TDB_INTERNAL"
         }
     }
 }

features/storage/kvstore/conf/tdb_internal/mbed_lib.json

@@ -18,6 +18,10 @@
         "CY8CKIT_062_WIFI_BT_M0_PSA": {
             "internal_size": "0x8000",
             "internal_base_address": "0x10078000"
+        },
+        "LPC55S69_S": {
+            "internal_size": "0x10000",
+            "internal_base_address": "0x00030000"
         }
     }
 }

platform/mbed_wait_api_no_rtos.c

@@ -51,10 +51,12 @@ void wait_us(int us)
 // Cortex-M0 and Cortex-M1 take 6 cycles per iteration - SUBS = 1, 2xNOP = 2, BCS = 3
 #define LOOP_SCALER 6000
 #elif (__CORTEX_M == 0 && defined __CM0PLUS_REV) || __CORTEX_M == 3 || __CORTEX_M == 4 || \
-      __CORTEX_M == 23 || __CORTEX_M == 33
-// Cortex-M0+, M3, M4, M23 and M33 take 5 cycles per iteration - SUBS = 1, 2xNOP = 2, BCS = 2
-// TODO - check M33
+      __CORTEX_M == 23
+// Cortex-M0+, M3, M4 and M23 take 5 cycles per iteration - SUBS = 1, 2xNOP = 2, BCS = 2
 #define LOOP_SCALER 5000
+#elif __CORTEX_M == 33
+// Cortex-M33 can dual issue for 3 cycles per iteration (SUB,NOP) = 1, (NOP,BCS) = 2
+#define LOOP_SCALER 3000
 #elif __CORTEX_M == 7
 // Cortex-M7 manages to dual-issue for 2 cycles per iteration (SUB,NOP) = 1, (NOP,BCS) = 1
 // (The NOPs were added to stabilise this - with just the SUB and BCS, it seems that the

targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC/analogin_api.c

@@ -16,7 +16,7 @@
 #include "mbed_assert.h"
 #include "analogin_api.h"
 
-#if DEVICE_ANALOGIN
+#if DEVICE_ANALOGIN && !defined(NXP_LPADC)
 
 #include "cmsis.h"
 #include "pinmap.h"

targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC/gpio_api.c

@@ -62,7 +62,7 @@ void gpio_write(gpio_t *obj, int value)
     uint32_t pin_number = obj->pin & 0x1F;
     uint8_t port_number = obj->pin / 32;
 
-    GPIO_WritePinOutput(GPIO, port_number, pin_number, value);
+    GPIO_PinWrite(GPIO, port_number, pin_number, value);
 }
 
 int gpio_read(gpio_t *obj)
@@ -71,5 +71,5 @@ int gpio_read(gpio_t *obj)
     uint32_t pin_number = obj->pin & 0x1F;
     uint8_t port_number = obj->pin / 32;
 
-    return (int)GPIO_ReadPinInput(GPIO, port_number, pin_number);
+    return (int)GPIO_PinRead(GPIO, port_number, pin_number);
 }

targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC/i2c_api.c

@@ -69,13 +69,13 @@ void i2c_init(i2c_t *obj, PinName sda, PinName scl)
             CLOCK_AttachClk(kFRO12M_to_FLEXCOMM7);
             RESET_PeripheralReset(kFC7_RST_SHIFT_RSTn);
             break;
-#if (FSL_FEATURE_SOC_FLEXCOMM_COUNT > 8U)
+#if (FSL_FEATURE_SOC_I2C_COUNT > 8U)
         case 8:
             CLOCK_AttachClk(kFRO12M_to_FLEXCOMM8);
             RESET_PeripheralReset(kFC8_RST_SHIFT_RSTn);
             break;
 #endif
-#if (FSL_FEATURE_SOC_FLEXCOMM_COUNT > 9U)
+#if (FSL_FEATURE_SOC_I2C_COUNT > 9U)
         case 9:
             CLOCK_AttachClk(kFRO12M_to_FLEXCOMM9);
             RESET_PeripheralReset(kFC9_RST_SHIFT_RSTn);

targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC/lp_analogin_api.c

@@ -0,0 +1,148 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "mbed_assert.h"
+#include "analogin_api.h"
+
+#if DEVICE_ANALOGIN && defined(NXP_LPADC)
+
+#include "cmsis.h"
+#include "pinmap.h"
+#include "gpio_api.h"
+#include "PeripheralNames.h"
+#include "fsl_lpadc.h"
+#include "fsl_power.h"
+#include "PeripheralPins.h"
+
+/* Array of ADC peripheral base address. */
+static ADC_Type *const adc_addrs[] = ADC_BASE_PTRS;
+extern void ADC_ClockPower_Configuration(void);
+
+#define LPADC_USER_CMDID 1U /* CMD1 */
+
+void analogin_init(analogin_t *obj, PinName pin)
+{
+    gpio_t gpio;
+
+    obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC);
+    MBED_ASSERT(obj->adc != (ADCName)NC);
+
+    uint32_t instance = obj->adc >> ADC_INSTANCE_SHIFT;
+    lpadc_config_t adc_config;
+    uint32_t reg;
+    uint32_t pin_number = pin & 0x1F;
+    uint8_t port_number = pin / 32;
+
+    ADC_ClockPower_Configuration();
+
+    LPADC_GetDefaultConfig(&adc_config);
+    adc_config.enableAnalogPreliminary = true;
+#if defined(LPADC_VREF_SOURCE)
+    adc_config.referenceVoltageSource = LPADC_VREF_SOURCE;
+#endif
+#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS
+    adc_config.conversionAverageMode = kLPADC_ConversionAverage128;
+#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS */
+    LPADC_Init(adc_addrs[instance], &adc_config);
+
+#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CALOFS) && FSL_FEATURE_LPADC_HAS_CTRL_CALOFS
+#if defined(FSL_FEATURE_LPADC_HAS_OFSTRIM) && FSL_FEATURE_LPADC_HAS_OFSTRIM
+    /* Request offset calibration. */
+    if (true == LPADC_DO_OFFSET_CALIBRATION) {
+        LPADC_DoOffsetCalibration(adc_addrs[instance]);
+    } else {
+        LPADC_SetOffsetValue(adc_addrs[instance], LPADC_OFFSET_VALUE_A, LPADC_OFFSET_VALUE_B);
+    }
+#endif /* FSL_FEATURE_LPADC_HAS_OFSTRIM */
+    /* Request gain calibration. */
+    LPADC_DoAutoCalibration(adc_addrs[instance]);
+#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CALOFS */
+
+#if (defined(FSL_FEATURE_LPADC_HAS_CFG_CALOFS) && FSL_FEATURE_LPADC_HAS_CFG_CALOFS)
+    /* Do auto calibration. */
+    LPADC_DoAutoCalibration(adc_addrs[instance]);
+#endif /* FSL_FEATURE_LPADC_HAS_CFG_CALOFS */
+
+    pinmap_pinout(pin, PinMap_ADC);
+
+    reg = IOCON->PIO[port_number][pin_number];
+    /* Clear the DIGIMODE bit */
+    reg &= ~IOCON_PIO_DIGIMODE_MASK;
+    /* For pins PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and
+       PIO1_9, leave ASW bit at '0' in the related IOCON register. */
+    if (((port_number == 0) && ((pin_number == 9) || (pin_number == 11) || (pin_number == 12) ||
+                                (pin_number == 15) || (pin_number == 18) || (pin_number == 31))) ||
+       ((port_number == 1) && ((pin_number == 0) || (pin_number == 9)))) {
+        /* Disable Analog Switch Input control */
+        reg &= ~IOCON_PIO_ASW_MASK;
+    } else {
+        /* Enable Analog Switch Input control */
+        reg |= IOCON_PIO_ASW_MASK;
+    }
+    IOCON->PIO[port_number][pin_number] = reg;
+
+    /* Need to ensure the pin is in input mode */
+    gpio_init(&gpio, pin);
+    gpio_dir(&gpio, PIN_INPUT);
+}
+
+uint16_t analogin_read_u16(analogin_t *obj)
+{
+    uint32_t instance = obj->adc >> ADC_INSTANCE_SHIFT;
+    uint32_t channel = obj->adc & 0xF;
+    lpadc_conv_trigger_config_t mLpadcTriggerConfigStruct;
+    lpadc_conv_command_config_t mLpadcCommandConfigStruct;
+    lpadc_conv_result_t mLpadcResultConfigStruct;
+
+    memset(&mLpadcTriggerConfigStruct, 0, sizeof(mLpadcTriggerConfigStruct));
+    memset(&mLpadcCommandConfigStruct, 0, sizeof(mLpadcCommandConfigStruct));
+    memset(&mLpadcResultConfigStruct, 0, sizeof(mLpadcResultConfigStruct));
+
+    /* Set conversion CMD configuration. */
+    LPADC_GetDefaultConvCommandConfig(&mLpadcCommandConfigStruct);
+    mLpadcCommandConfigStruct.channelNumber = channel;
+    LPADC_SetConvCommandConfig(adc_addrs[instance], LPADC_USER_CMDID, &mLpadcCommandConfigStruct);
+
+    /* Set trigger configuration. */
+    LPADC_GetDefaultConvTriggerConfig(&mLpadcTriggerConfigStruct);
+    mLpadcTriggerConfigStruct.targetCommandId = LPADC_USER_CMDID;
+    mLpadcTriggerConfigStruct.enableHardwareTrigger = false;
+    LPADC_SetConvTriggerConfig(adc_addrs[instance], 0U, &mLpadcTriggerConfigStruct); /* Configurate the trigger0. */
+
+    LPADC_DoSoftwareTrigger(adc_addrs[instance], 1U); /* 1U is trigger0 mask. */
+
+#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2U))
+    while (!LPADC_GetConvResult(adc_addrs[instance], &mLpadcResultConfigStruct, 0U)) {
+    }
+#else
+    while (!LPADC_GetConvResult(adc_addrs[instance], &mLpadcResultConfigStruct)) {
+    }
+#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */
+
+    return ((mLpadcResultConfigStruct.convValue) >> 3U);
+}
+
+float analogin_read(analogin_t *obj)
+{
+    uint16_t value = analogin_read_u16(obj);
+    return (float)value * (1.0f / (float)0xFFFF);
+}
+
+const PinMap *analogin_pinmap()
+{
+    return PinMap_ADC;
+}
+
+#endif

targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC/objects.h

@@ -59,7 +59,7 @@ struct spi_s {
     uint8_t bits;
 };
 
-#if DEVICE_FLASH
+#if DEVICE_FLASH && !defined(TARGET_FLASH_CMSIS_ALGO)
 struct flash_s {
     uint8_t dummy;
 };

targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC/pinmap.c

@@ -33,7 +33,7 @@ void pin_function(PinName pin, int function)
     IOCON->PIO[port_number][pin_number] |= IOCON_PIO_DIGIMODE_MASK;
 
     reg = IOCON->PIO[port_number][pin_number];
-    reg = (reg & ~0x7) | (function & 0x7);
+    reg = (reg & ~0x7) | (function & IOCON_PIO_FUNC_MASK);
     IOCON->PIO[port_number][pin_number] = reg;
 }
 

targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC/port_api.c

@@ -71,12 +71,12 @@ void port_dir(port_t *obj, PinDirection dir)
 
 void port_write(port_t *obj, int value)
 {
-    GPIO_WriteMPort(GPIO, obj->port, value);
+    GPIO_PortMaskedWrite(GPIO, obj->port, value);
 }
 
 int port_read(port_t *obj)
 {
-    return (int)(GPIO_ReadMPort(GPIO, obj->port));
+    return (int)(GPIO_PortMaskedRead(GPIO, obj->port));
 }
 
 #endif

targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC/serial_api.c

@@ -79,13 +79,13 @@ void serial_init(serial_t *obj, PinName tx, PinName rx)
             CLOCK_AttachClk(kFRO12M_to_FLEXCOMM7);
             RESET_PeripheralReset(kFC7_RST_SHIFT_RSTn);
             break;
-#if (FSL_FEATURE_SOC_FLEXCOMM_COUNT > 8U)
+#if (FSL_FEATURE_SOC_USART_COUNT > 8U)
         case 8:
             CLOCK_AttachClk(kFRO12M_to_FLEXCOMM8);
             RESET_PeripheralReset(kFC8_RST_SHIFT_RSTn);
             break;
 #endif
-#if (FSL_FEATURE_SOC_FLEXCOMM_COUNT > 9U)
+#if (FSL_FEATURE_SOC_USART_COUNT > 9U)
         case 9:
             CLOCK_AttachClk(kFRO12M_to_FLEXCOMM9);
             RESET_PeripheralReset(kFC9_RST_SHIFT_RSTn);
@@ -225,15 +225,15 @@ void uart7_irq()
     uart_irq((status_flags & kUSART_TxFifoEmptyFlag), (status_flags & kUSART_RxFifoNotEmptyFlag), 7);
 }
 
-#if (FSL_FEATURE_SOC_FLEXCOMM_COUNT > 8U)
+#if (FSL_FEATURE_SOC_USART_COUNT > 8U)
 void uart8_irq()
 {
     uint32_t status_flags = USART8->FIFOSTAT;
     uart_irq((status_flags & kUSART_TxFifoEmptyFlag), (status_flags & kUSART_RxFifoNotEmptyFlag), 8);
 }
 #endif
 
-#if (FSL_FEATURE_SOC_FLEXCOMM_COUNT > 9U)
+#if (FSL_FEATURE_SOC_USART_COUNT > 9U)
 void uart9_irq()
 {
     uint32_t status_flags = USART9->FIFOSTAT;
@@ -277,12 +277,12 @@ void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable)
         case 7:
             vector = (uint32_t)&uart7_irq;
             break;
-#if (FSL_FEATURE_SOC_FLEXCOMM_COUNT > 8U)
+#if (FSL_FEATURE_SOC_USART_COUNT > 8U)
         case 8:
             vector = (uint32_t)&uart8_irq;
             break;
 #endif
-#if (FSL_FEATURE_SOC_FLEXCOMM_COUNT > 9U)
+#if (FSL_FEATURE_SOC_USART_COUNT > 9U)
         case 9:
             vector = (uint32_t)&uart9_irq;
             break;

targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC/sleep.c

@@ -27,7 +27,13 @@ void hal_sleep(void)
 void hal_deepsleep(void)
 {
     LPC_CLOCK_INTERNAL_IRC;
+
     /* Enter Deep Sleep mode */
+#if (defined(FSL_FEATURE_POWERLIB_NIOBE4_EXTEND ) && FSL_FEATURE_POWERLIB_NIOBE4_EXTEND )
+    POWER_EnterDeepSleep(APP_EXCLUDE_FROM_DEEPSLEEP, 0x0, WAKEUP_GPIO_INT0_0, 0x0);
+#else
     POWER_EnterDeepSleep(APP_EXCLUDE_FROM_DEEPSLEEP);
+#endif
+
     LPC_CLOCK_RUN;
 }