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Cruz Monrreal
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Merge pull request #9232 from ChazJin/gd32f450
Add GD32_F450ZI as new target
2 parents d20b591 + 970bc24 commit 12980f4

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‎features/netsocket/emac-drivers/TARGET_GD_EMAC/TARGET_GD32F4XX/gd32f4_eth_init.c

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/* mbed Microcontroller Library
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* Copyright (c) 2018 GigaDevice Semiconductor Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include "gd32f4xx.h"
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/**
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* Initializes the HW pin for enet
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*
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*/
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void enet_bsp_init(void)
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{
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/* enable GPIOs clocks */
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rcu_periph_clock_enable(RCU_GPIOA);
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rcu_periph_clock_enable(RCU_GPIOB);
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rcu_periph_clock_enable(RCU_GPIOC);
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/* enable SYSCFG clock */
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rcu_periph_clock_enable(RCU_SYSCFG);
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syscfg_enet_phy_interface_config(SYSCFG_ENET_PHY_RMII);
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/** ETH GPIO Configuration
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RMII_REF_CLK ----------------------> PA1
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RMII_MDIO -------------------------> PA2
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RMII_MDC --------------------------> PC1
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RMII_MII_CRS_DV -------------------> PA7
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RMII_MII_RXD0 ---------------------> PC4
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RMII_MII_RXD1 ---------------------> PC5
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RMII_MII_TX_EN --------------------> PB11
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RMII_MII_TXD0 ---------------------> PB12
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RMII_MII_TXD1 ---------------------> PB13
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*/
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/* PA1: ETH_RMII_REF_CLK */
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gpio_mode_set(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_1);
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gpio_output_options_set(GPIOA, GPIO_OTYPE_PP, GPIO_OSPEED_200MHZ, GPIO_PIN_1);
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/* PA2: ETH_MDIO */
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gpio_mode_set(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_2);
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gpio_output_options_set(GPIOA, GPIO_OTYPE_PP, GPIO_OSPEED_200MHZ, GPIO_PIN_2);
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/* PA7: ETH_RMII_CRS_DV */
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gpio_mode_set(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_7);
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gpio_output_options_set(GPIOA, GPIO_OTYPE_PP, GPIO_OSPEED_200MHZ, GPIO_PIN_7);
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gpio_af_set(GPIOA, GPIO_AF_11, GPIO_PIN_1);
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gpio_af_set(GPIOA, GPIO_AF_11, GPIO_PIN_2);
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gpio_af_set(GPIOA, GPIO_AF_11, GPIO_PIN_7);
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/* PB11: ETH_RMII_TX_EN */
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gpio_mode_set(GPIOB, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_11);
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gpio_output_options_set(GPIOB, GPIO_OTYPE_PP, GPIO_OSPEED_200MHZ, GPIO_PIN_11);
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/* PB12: ETH_RMII_TXD0 */
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gpio_mode_set(GPIOB, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_12);
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gpio_output_options_set(GPIOB, GPIO_OTYPE_PP, GPIO_OSPEED_200MHZ, GPIO_PIN_12);
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/* PB13: ETH_RMII_TXD1 */
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gpio_mode_set(GPIOB, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_13);
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gpio_output_options_set(GPIOB, GPIO_OTYPE_PP, GPIO_OSPEED_200MHZ, GPIO_PIN_13);
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gpio_af_set(GPIOB, GPIO_AF_11, GPIO_PIN_11);
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gpio_af_set(GPIOB, GPIO_AF_11, GPIO_PIN_12);
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gpio_af_set(GPIOB, GPIO_AF_11, GPIO_PIN_13);
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/* PC1: ETH_MDC */
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gpio_mode_set(GPIOC, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_1);
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gpio_output_options_set(GPIOC, GPIO_OTYPE_PP, GPIO_OSPEED_200MHZ, GPIO_PIN_1);
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/* PC4: ETH_RMII_RXD0 */
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gpio_mode_set(GPIOC, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_4);
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gpio_output_options_set(GPIOC, GPIO_OTYPE_PP, GPIO_OSPEED_200MHZ, GPIO_PIN_4);
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/* PC5: ETH_RMII_RXD1 */
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gpio_mode_set(GPIOC, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_5);
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gpio_output_options_set(GPIOC, GPIO_OTYPE_PP, GPIO_OSPEED_200MHZ, GPIO_PIN_5);
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gpio_af_set(GPIOC, GPIO_AF_11, GPIO_PIN_1);
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gpio_af_set(GPIOC, GPIO_AF_11, GPIO_PIN_4);
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gpio_af_set(GPIOC, GPIO_AF_11, GPIO_PIN_5);
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/* enable the ETHERNET global interrupt */
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nvic_irq_enable(ENET_IRQn, 0x7, 0);
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/* enable ETHERNET clock */
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rcu_periph_clock_enable(RCU_ENET);
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rcu_periph_clock_enable(RCU_ENETTX);
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rcu_periph_clock_enable(RCU_ENETRX);
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}

‎targets/TARGET_GigaDevice/TARGET_GD32F4XX/GD32F4xx_standard_peripheral/Include/gd32f4xx_adc.h

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‎targets/TARGET_GigaDevice/TARGET_GD32F4XX/GD32F4xx_standard_peripheral/Include/gd32f4xx_can.h

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‎targets/TARGET_GigaDevice/TARGET_GD32F4XX/GD32F4xx_standard_peripheral/Include/gd32f4xx_crc.h

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/*!
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\file gd32f4xx_crc.h
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\brief definitions for the CRC
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\version 2016-08-15, V1.0.0, firmware for GD32F4xx
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\version 2018-12-12, V2.0.0, firmware for GD32F4xx
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\version 2018-12-25, V2.1.0, firmware for GD32F4xx (The version is for mbed)
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*/
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/*
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Copyright (c) 2018, GigaDevice Semiconductor Inc.
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All rights reserved.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice, this
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list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation
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and/or other materials provided with the distribution.
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3. Neither the name of the copyright holder nor the names of its contributors
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may be used to endorse or promote products derived from this software without
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specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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OF SUCH DAMAGE.
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*/
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#ifndef GD32F4XX_CRC_H
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#define GD32F4XX_CRC_H
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#include "gd32f4xx.h"
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/* CRC definitions */
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#define CRC CRC_BASE
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/* registers definitions */
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#define CRC_DATA REG32(CRC + 0x00U) /*!< CRC data register */
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#define CRC_FDATA REG32(CRC + 0x04U) /*!< CRC free data register */
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#define CRC_CTL REG32(CRC + 0x08U) /*!< CRC control register */
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/* bits definitions */
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/* CRC_DATA */
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#define CRC_DATA_DATA BITS(0,31) /*!< CRC calculation result bits */
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/* CRC_FDATA */
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#define CRC_FDATA_FDATA BITS(0,7) /*!< CRC free data bits */
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/* CRC_CTL */
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#define CRC_CTL_RST BIT(0) /*!< CRC reset CRC_DATA register bit */
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/* function declarations */
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/* deinit CRC calculation unit */
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void crc_deinit(void);
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/* reset data register(CRC_DATA) to the value of 0xFFFFFFFF */
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void crc_data_register_reset(void);
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/* read the value of the data register */
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uint32_t crc_data_register_read(void);
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/* read the value of the free data register */
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uint8_t crc_free_data_register_read(void);
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/* write data to the free data register */
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void crc_free_data_register_write(uint8_t free_data);
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/* calculate the CRC value of a 32-bit data */
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uint32_t crc_single_data_calculate(uint32_t sdata);
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/* calculate the CRC value of an array of 32-bit values */
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uint32_t crc_block_data_calculate(uint32_t array[], uint32_t size);
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#endif /* GD32F4XX_CRC_H */

‎targets/TARGET_GigaDevice/TARGET_GD32F4XX/GD32F4xx_standard_peripheral/Include/gd32f4xx_ctc.h

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/*!
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\file gd32f4xx_ctc.h
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\brief definitions for the CTC
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\version 2016-08-15, V1.0.0, firmware for GD32F4xx
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\version 2018-12-12, V2.0.0, firmware for GD32F4xx
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\version 2018-12-25, V2.1.0, firmware for GD32F4xx (The version is for mbed)
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*/
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/*
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Copyright (c) 2018, GigaDevice Semiconductor Inc.
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All rights reserved.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice, this
19+
list of conditions and the following disclaimer.
20+
2. Redistributions in binary form must reproduce the above copyright notice,
21+
this list of conditions and the following disclaimer in the documentation
22+
and/or other materials provided with the distribution.
23+
3. Neither the name of the copyright holder nor the names of its contributors
24+
may be used to endorse or promote products derived from this software without
25+
specific prior written permission.
26+
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
28+
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
29+
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
30+
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
31+
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
33+
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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OF SUCH DAMAGE.
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*/
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#ifndef GD32F4XX_CTC_H
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#define GD32F4XX_CTC_H
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#include "gd32f4xx.h"
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/* CTC definitions */
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#define CTC CTC_BASE
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/* registers definitions */
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#define CTC_CTL0 REG32((CTC) + 0x00U) /*!< CTC control register 0 */
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#define CTC_CTL1 REG32((CTC) + 0x04U) /*!< CTC control register 1 */
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#define CTC_STAT REG32((CTC) + 0x08U) /*!< CTC status register */
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#define CTC_INTC REG32((CTC) + 0x0CU) /*!< CTC interrupt clear register */
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/* bits definitions */
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/* CTC_CTL0 */
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#define CTC_CTL0_CKOKIE BIT(0) /*!< clock trim OK(CKOKIF) interrupt enable */
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#define CTC_CTL0_CKWARNIE BIT(1) /*!< clock trim warning(CKWARNIF) interrupt enable */
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#define CTC_CTL0_ERRIE BIT(2) /*!< error(ERRIF) interrupt enable */
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#define CTC_CTL0_EREFIE BIT(3) /*!< EREFIF interrupt enable */
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#define CTC_CTL0_CNTEN BIT(5) /*!< CTC counter enable */
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#define CTC_CTL0_AUTOTRIM BIT(6) /*!< hardware automatically trim mode */
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#define CTC_CTL0_SWREFPUL BIT(7) /*!< software reference source sync pulse */
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#define CTC_CTL0_TRIMVALUE BITS(8,13) /*!< IRC48M trim value */
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/* CTC_CTL1 */
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#define CTC_CTL1_RLVALUE BITS(0,15) /*!< CTC counter reload value */
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#define CTC_CTL1_CKLIM BITS(16,23) /*!< clock trim base limit value */
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#define CTC_CTL1_REFPSC BITS(24,26) /*!< reference signal source prescaler */
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#define CTC_CTL1_REFSEL BITS(28,29) /*!< reference signal source selection */
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#define CTC_CTL1_USBSOFSEL BIT(30) /*!< USBFS or USBHS SOF signal selection */
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#define CTC_CTL1_REFPOL BIT(31) /*!< reference signal source polarity */
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/* CTC_STAT */
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#define CTC_STAT_CKOKIF BIT(0) /*!< clock trim OK interrupt flag */
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#define CTC_STAT_CKWARNIF BIT(1) /*!< clock trim warning interrupt flag */
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#define CTC_STAT_ERRIF BIT(2) /*!< error interrupt flag */
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#define CTC_STAT_EREFIF BIT(3) /*!< expect reference interrupt flag */
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#define CTC_STAT_CKERR BIT(8) /*!< clock trim error bit */
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#define CTC_STAT_REFMISS BIT(9) /*!< reference sync pulse miss */
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#define CTC_STAT_TRIMERR BIT(10) /*!< trim value error bit */
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#define CTC_STAT_REFDIR BIT(15) /*!< CTC trim counter direction when reference sync pulse occurred */
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#define CTC_STAT_REFCAP BITS(16,31) /*!< CTC counter capture when reference sync pulse occurred */
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/* CTC_INTC */
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#define CTC_INTC_CKOKIC BIT(0) /*!< CKOKIF interrupt clear bit */
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#define CTC_INTC_CKWARNIC BIT(1) /*!< CKWARNIF interrupt clear bit */
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#define CTC_INTC_ERRIC BIT(2) /*!< ERRIF interrupt clear bit */
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#define CTC_INTC_EREFIC BIT(3) /*!< EREFIF interrupt clear bit */
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/* constants definitions */
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/* hardware automatically trim mode definitions */
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#define CTC_HARDWARE_TRIM_MODE_ENABLE CTC_CTL0_AUTOTRIM /*!< hardware automatically trim mode enable*/
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#define CTC_HARDWARE_TRIM_MODE_DISABLE ((uint32_t)0x00000000U) /*!< hardware automatically trim mode disable*/
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/* reference signal source polarity definitions */
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#define CTC_REFSOURCE_POLARITY_FALLING CTC_CTL1_REFPOL /*!< reference signal source polarity is falling edge*/
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#define CTC_REFSOURCE_POLARITY_RISING ((uint32_t)0x00000000U) /*!< reference signal source polarity is rising edge*/
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/* USBFS or USBHS SOF signal selection definitions */
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#define CTC_USBSOFSEL_USBHS CTC_CTL1_USBSOFSEL /*!< USBHS SOF signal is selected*/
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#define CTC_USBSOFSEL_USBFS ((uint32_t)0x00000000U) /*!< USBFS SOF signal is selected*/
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/* reference signal source selection definitions */
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#define CTL1_REFSEL(regval) (BITS(28,29) & ((uint32_t)(regval) << 28))
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#define CTC_REFSOURCE_GPIO CTL1_REFSEL(0) /*!< GPIO is selected */
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#define CTC_REFSOURCE_LXTAL CTL1_REFSEL(1) /*!< LXTAL is clock selected */
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#define CTC_REFSOURCE_USBSOF CTL1_REFSEL(2) /*!< USBSOF is selected */
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/* reference signal source prescaler definitions */
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#define CTL1_REFPSC(regval) (BITS(24,26) & ((uint32_t)(regval) << 24))
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#define CTC_REFSOURCE_PSC_OFF CTL1_REFPSC(0) /*!< reference signal not divided */
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#define CTC_REFSOURCE_PSC_DIV2 CTL1_REFPSC(1) /*!< reference signal divided by 2 */
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#define CTC_REFSOURCE_PSC_DIV4 CTL1_REFPSC(2) /*!< reference signal divided by 4 */
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#define CTC_REFSOURCE_PSC_DIV8 CTL1_REFPSC(3) /*!< reference signal divided by 8 */
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#define CTC_REFSOURCE_PSC_DIV16 CTL1_REFPSC(4) /*!< reference signal divided by 16 */
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#define CTC_REFSOURCE_PSC_DIV32 CTL1_REFPSC(5) /*!< reference signal divided by 32 */
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#define CTC_REFSOURCE_PSC_DIV64 CTL1_REFPSC(6) /*!< reference signal divided by 64 */
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#define CTC_REFSOURCE_PSC_DIV128 CTL1_REFPSC(7) /*!< reference signal divided by 128 */
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/* CTC interrupt enable definitions */
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#define CTC_INT_CKOK CTC_CTL0_CKOKIE /*!< clock trim OK interrupt enable */
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#define CTC_INT_CKWARN CTC_CTL0_CKWARNIE /*!< clock trim warning interrupt enable */
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#define CTC_INT_ERR CTC_CTL0_ERRIE /*!< error interrupt enable */
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#define CTC_INT_EREF CTC_CTL0_EREFIE /*!< expect reference interrupt enable */
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/* CTC interrupt source definitions */
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#define CTC_INT_FLAG_CKOK CTC_STAT_CKOKIF /*!< clock trim OK interrupt flag */
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#define CTC_INT_FLAG_CKWARN CTC_STAT_CKWARNIF /*!< clock trim warning interrupt flag */
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#define CTC_INT_FLAG_ERR CTC_STAT_ERRIF /*!< error interrupt flag */
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#define CTC_INT_FLAG_EREF CTC_STAT_EREFIF /*!< expect reference interrupt flag */
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#define CTC_INT_FLAG_CKERR CTC_STAT_CKERR /*!< clock trim error bit */
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#define CTC_INT_FLAG_REFMISS CTC_STAT_REFMISS /*!< reference sync pulse miss */
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#define CTC_INT_FLAG_TRIMERR CTC_STAT_TRIMERR /*!< trim value error */
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/* CTC flag definitions */
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#define CTC_FLAG_CKOK CTC_STAT_CKOKIF /*!< clock trim OK flag */
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#define CTC_FLAG_CKWARN CTC_STAT_CKWARNIF /*!< clock trim warning flag */
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#define CTC_FLAG_ERR CTC_STAT_ERRIF /*!< error flag */
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#define CTC_FLAG_EREF CTC_STAT_EREFIF /*!< expect reference flag */
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#define CTC_FLAG_CKERR CTC_STAT_CKERR /*!< clock trim error bit */
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#define CTC_FLAG_REFMISS CTC_STAT_REFMISS /*!< reference sync pulse miss */
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#define CTC_FLAG_TRIMERR CTC_STAT_TRIMERR /*!< trim value error bit */
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/* function declarations */
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/* reset ctc clock trim controller */
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void ctc_deinit(void);
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/* enable CTC trim counter */
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void ctc_counter_enable(void);
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/* disable CTC trim counter */
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void ctc_counter_disable(void);
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/* configure the IRC48M trim value */
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void ctc_irc48m_trim_value_config(uint8_t trim_value);
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/* generate software reference source sync pulse */
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void ctc_software_refsource_pulse_generate(void);
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/* configure hardware automatically trim mode */
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void ctc_hardware_trim_mode_config(uint32_t hardmode);
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/* configure reference signal source polarity */
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void ctc_refsource_polarity_config(uint32_t polarity);
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/* select USBFS or USBHS SOF signal */
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void ctc_usbsof_signal_select(uint32_t usbsof);
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/* select reference signal source */
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void ctc_refsource_signal_select(uint32_t refs);
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/* configure reference signal source prescaler */
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void ctc_refsource_prescaler_config(uint32_t prescaler);
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/* configure clock trim base limit value */
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void ctc_clock_limit_value_config(uint8_t limit_value);
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/* configure CTC counter reload value */
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void ctc_counter_reload_value_config(uint16_t reload_value);
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/* read CTC counter capture value when reference sync pulse occurred */
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uint16_t ctc_counter_capture_value_read(void);
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/* read CTC trim counter direction when reference sync pulse occurred */
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FlagStatus ctc_counter_direction_read(void);
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/* read CTC counter reload value */
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uint16_t ctc_counter_reload_value_read(void);
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/* read the IRC48M trim value */
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uint8_t ctc_irc48m_trim_value_read(void);
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/* interrupt & flag functions */
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/* enable the CTC interrupt */
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void ctc_interrupt_enable(uint32_t interrupt);
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/* disable the CTC interrupt */
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void ctc_interrupt_disable(uint32_t interrupt);
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/* get CTC interrupt flag */
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FlagStatus ctc_interrupt_flag_get(uint32_t int_flag);
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/* clear CTC interrupt flag */
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void ctc_interrupt_flag_clear(uint32_t int_flag);
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/* get CTC flag */
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FlagStatus ctc_flag_get(uint32_t flag);
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/* clear CTC flag */
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void ctc_flag_clear(uint32_t flag);
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#endif /* GD32F4XX_CTC_H */

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