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DISCO_L053C8: enable HSI48 clock for USB
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-3
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targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/device/system_stm32l0xx.c

Lines changed: 7 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -377,10 +377,8 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
377377
RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */
378378
}
379379
RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
380-
#if !defined (STM32L031xx) && !defined (STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) && \
381-
!defined (STM32L011xx) && !defined (STM32L021xx)
382380
RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; /* For USB and RNG clock */
383-
#endif
381+
384382
// PLLCLK = (8 MHz * 8)/2 = 32 MHz
385383
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
386384
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
@@ -391,6 +389,12 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
391389
return 0; // FAIL
392390
}
393391

392+
/* Select HSI48 as USB clock source */
393+
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
394+
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
395+
PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;
396+
HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
397+
394398
/* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
395399
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
396400
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 32 MHz

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