Skip to content

Commit 142db46

Browse files
dreschpedreschpe
committed
Add additional peripherie definitions for ST Nucleo F401RE bord
add UART 2 + 3 add SPI 2 + 3 add I2C 2 + 3 patch SPI 16 bit error patch extenal cristal value to 8MHz
1 parent 74e9b2e commit 142db46

File tree

6 files changed

+86
-14
lines changed

6 files changed

+86
-14
lines changed

‎libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f401xe.h

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -678,15 +678,15 @@ USB_OTG_HostChannelTypeDef;
678678
*/
679679
#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH(up to 1 MB) base address in the alias region */
680680
#define CCMDATARAM_BASE ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */
681-
#define SRAM1_BASE ((uint32_t)0x20000000) /*!< SRAM1(112 KB) base address in the alias region */
682-
#define SRAM2_BASE ((uint32_t)0x2001C000) /*!< SRAM2(16 KB) base address in the alias region */
683-
#define SRAM3_BASE ((uint32_t)0x20020000) /*!< SRAM3(64 KB) base address in the alias region */
681+
#define SRAM1_BASE ((uint32_t)0x20000000) /*!< SRAM1(96 KB) base address in the alias region */
682+
//#define SRAM2_BASE ((uint32_t)0x2001C000) /*!< SRAM2(16 KB) base address in the alias region */
683+
//#define SRAM3_BASE ((uint32_t)0x20020000) /*!< SRAM3(64 KB) base address in the alias region */
684684
#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
685685
#define BKPSRAM_BASE ((uint32_t)0x40024000) /*!< Backup SRAM(4 KB) base address in the alias region */
686686
#define CCMDATARAM_BB_BASE ((uint32_t)0x12000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the bit-band region */
687-
#define SRAM1_BB_BASE ((uint32_t)0x22000000) /*!< SRAM1(112 KB) base address in the bit-band region */
688-
#define SRAM2_BB_BASE ((uint32_t)0x2201C000) /*!< SRAM2(16 KB) base address in the bit-band region */
689-
#define SRAM3_BB_BASE ((uint32_t)0x22020000) /*!< SRAM3(64 KB) base address in the bit-band region */
687+
#define SRAM1_BB_BASE ((uint32_t)0x22000000) /*!< SRAM1(96 KB) base address in the bit-band region */
688+
//#define SRAM2_BB_BASE ((uint32_t)0x2201C000) /*!< SRAM2(16 KB) base address in the bit-band region */
689+
//#define SRAM3_BB_BASE ((uint32_t)0x22020000) /*!< SRAM3(64 KB) base address in the bit-band region */
690690
#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
691691
#define BKPSRAM_BB_BASE ((uint32_t)0x42024000) /*!< Backup SRAM(4 KB) base address in the bit-band region */
692692

‎libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_conf.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -99,7 +99,7 @@
9999
* (when HSE is used as system clock source, directly or through the PLL).
100100
*/
101101
#if !defined (HSE_VALUE)
102-
#define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */
102+
#define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External crystal in Hz */
103103
#endif /* HSE_VALUE */
104104

105105
#if !defined (HSE_STARTUP_TIMEOUT)

‎libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PeripheralNames.h

Lines changed: 5 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -44,6 +44,7 @@ typedef enum {
4444
typedef enum {
4545
UART_1 = (int)USART1_BASE,
4646
UART_2 = (int)USART2_BASE
47+
UART_3 = (int)USART6_BASE,
4748
} UARTName;
4849

4950
#define STDIO_UART_TX PA_2
@@ -52,12 +53,14 @@ typedef enum {
5253

5354
typedef enum {
5455
SPI_1 = (int)SPI1_BASE,
55-
SPI_2 = (int)SPI2_BASE
56+
SPI_2 = (int)SPI2_BASE,
57+
SPI_3 = (int)SPI3_BASE
5658
} SPIName;
5759

5860
typedef enum {
5961
I2C_1 = (int)I2C1_BASE,
60-
I2C_2 = (int)I2C2_BASE
62+
I2C_2 = (int)I2C2_BASE,
63+
I2C_3 = (int)I2C3_BASE
6164
} I2CName;
6265

6366
typedef enum {

‎libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/i2c_api.c

Lines changed: 19 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -44,11 +44,15 @@
4444

4545
static const PinMap PinMap_I2C_SDA[] = {
4646
{PB_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
47+
{PB_3, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C2)},
48+
{PB_4, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C3)},
4749
{NC, NC, 0}
4850
};
4951

5052
static const PinMap PinMap_I2C_SCL[] = {
5153
{PB_8, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
54+
{PB_10, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
55+
{PA_8, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
5256
{NC, NC, 0}
5357
};
5458

@@ -69,6 +73,13 @@ void i2c_init(i2c_t *obj, PinName sda, PinName scl) {
6973
if (obj->i2c == I2C_1) {
7074
__I2C1_CLK_ENABLE();
7175
}
76+
if (obj->i2c == I2C_2) {
77+
__I2C2_CLK_ENABLE();
78+
}
79+
80+
if (obj->i2c == I2C_3) {
81+
__I2C3_CLK_ENABLE();
82+
}
7283

7384
// Configure I2C pins
7485
pinmap_pinout(sda, PinMap_I2C_SDA);
@@ -207,6 +218,14 @@ void i2c_reset(i2c_t *obj) {
207218
__I2C1_FORCE_RESET();
208219
__I2C1_RELEASE_RESET();
209220
}
221+
if (obj->i2c == I2C_2) {
222+
__I2C2_FORCE_RESET();
223+
__I2C2_RELEASE_RESET();
224+
}
225+
if (obj->i2c == I2C_3) {
226+
__I2C3_FORCE_RESET();
227+
__I2C3_RELEASE_RESET();
228+
}
210229
}
211230

212231
#if DEVICE_I2CSLAVE

‎libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/serial_api.c

Lines changed: 13 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -37,16 +37,18 @@
3737
static const PinMap PinMap_UART_TX[] = {
3838
{PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
3939
{PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
40+
{PC_6, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
4041
{NC, NC, 0}
4142
};
4243

4344
static const PinMap PinMap_UART_RX[] = {
4445
{PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
4546
{PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
47+
{PC_7, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
4648
{NC, NC, 0}
4749
};
4850

49-
#define UART_NUM (2)
51+
#define UART_NUM (3)
5052

5153
static uint32_t serial_irq_ids[UART_NUM] = {0};
5254

@@ -89,6 +91,9 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) {
8991
if (obj->uart == UART_2) {
9092
__USART2_CLK_ENABLE();
9193
}
94+
if (obj->uart == UART_3) {
95+
__USART6_CLK_ENABLE();
96+
}
9297

9398
// Configure the UART pins
9499
pinmap_pinout(tx, PinMap_UART_TX);
@@ -107,6 +112,7 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) {
107112
// The index is used by irq
108113
if (obj->uart == UART_1) obj->index = 0;
109114
if (obj->uart == UART_2) obj->index = 1;
115+
if (obj->uart == UART_3) obj->index = 2;
110116

111117
// For stdio management
112118
if (obj->uart == STDIO_UART) {
@@ -180,6 +186,7 @@ static void uart_irq(UARTName name, int id) {
180186
// Not part of mbed api
181187
static void uart1_irq(void) {uart_irq(UART_1, 0);}
182188
static void uart2_irq(void) {uart_irq(UART_2, 1);}
189+
static void uart3_irq(void) {uart_irq(UART_3, 2);}
183190

184191
void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) {
185192
irq_handler = handler;
@@ -202,6 +209,11 @@ void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) {
202209
vector = (uint32_t)&uart2_irq;
203210
}
204211

212+
if (obj->uart == UART_3) {
213+
irq_n = USART6_IRQn;
214+
vector = (uint32_t)&uart3_irq;
215+
}
216+
205217
if (enable) {
206218

207219
if (irq == RxIrq) {

‎libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/spi_api.c

Lines changed: 42 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -39,22 +39,42 @@
3939

4040
static const PinMap PinMap_SPI_MOSI[] = {
4141
{PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
42+
{PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
43+
{PC_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
44+
{PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
45+
{PC_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
46+
{PB_5 , SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
4247
{NC, NC, 0}
4348
};
4449

4550
static const PinMap PinMap_SPI_MISO[] = {
4651
{PA_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
52+
{PB_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
53+
{PC_2, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
54+
{PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
55+
{PC_11, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
56+
{PB_4 , SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
4757
{NC, NC, 0}
4858
};
4959

5060
static const PinMap PinMap_SPI_SCLK[] = {
5161
{PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
62+
{PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
63+
{PB_10, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
64+
{PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
65+
{PC_10, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
66+
{PB_3 , SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
5267
{NC, NC, 0}
5368
};
5469

5570
// Only used in Slave mode
5671
static const PinMap PinMap_SPI_SSEL[] = {
57-
{PB_6, SPI_1, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)}, // Generic IO, not real H/W NSS pin
72+
{PA_4, SPI_1, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, GPIO_AF5_SPI1)},
73+
{PA_15, SPI_1, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, GPIO_AF5_SPI1)},
74+
{PB_9 , SPI_2, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, GPIO_AF5_SPI2)},
75+
{PB_12, SPI_2, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, GPIO_AF5_SPI2)},
76+
{PA_4 , SPI_3, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, GPIO_AF6_SPI3)},
77+
{PA_15, SPI_3, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, GPIO_AF6_SPI3)},
5878
{NC, NC, 0}
5979
};
6080

@@ -102,19 +122,28 @@ void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel
102122
if (obj->spi == SPI_1) {
103123
__SPI1_CLK_ENABLE();
104124
}
125+
if (obj->spi == SPI_2) {
126+
__SPI2_CLK_ENABLE();
127+
}
128+
if (obj->spi == SPI_3) {
129+
__SPI3_CLK_ENABLE();
130+
}
105131

106132
// Configure the SPI pins
107133
pinmap_pinout(mosi, PinMap_SPI_MOSI);
108134
pinmap_pinout(miso, PinMap_SPI_MISO);
109135
pinmap_pinout(sclk, PinMap_SPI_SCLK);
136+
if (ssel != NC) { // slave mode
137+
pinmap_pinout(ssel, PinMap_SPI_SSEL);
138+
}
110139

111140
// Save new values
112141
obj->bits = SPI_DATASIZE_8BIT;
113142
obj->cpol = SPI_POLARITY_LOW;
114143
obj->cpha = SPI_PHASE_1EDGE;
115144
obj->br_presc = SPI_BAUDRATEPRESCALER_256; // 1MHz (with HSI=16MHz and APB2CLKDivider=2)
116145

117-
if (ssel == NC) { // Master
146+
if (ssel == NC) { // SW NSS Master mode
118147
obj->mode = SPI_MODE_MASTER;
119148
obj->nss = SPI_NSS_SOFT;
120149
}
@@ -174,8 +203,15 @@ void spi_format(spi_t *obj, int bits, int mode, int slave) {
174203

175204
void spi_frequency(spi_t *obj, int hz) {
176205
// Get SPI clock frequency
177-
uint32_t PCLK = SystemCoreClock >> 1;
178206

207+
// SPI1 runs from PCLK2, which runs at SystemCoreClock / 2. SPI2 and SPI3
208+
// run from PCLK1, which runs at SystemCoreClock / 4.
209+
uint32_t PCLK = SystemCoreClock;
210+
switch ((int)obj->spi) {
211+
case SPI_1: PCLK = PCLK >> 1; break;
212+
case SPI_2: PCLK = PCLK >> 2; break;
213+
case SPI_3: PCLK = PCLK >> 2; break;
214+
}
179215
// Choose the baud rate divisor (between 2 and 256)
180216
uint32_t divisor = PCLK / hz;
181217

@@ -215,7 +251,9 @@ static inline int ssp_writeable(spi_t *obj) {
215251
static inline void ssp_write(spi_t *obj, int value) {
216252
SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi);
217253
while (!ssp_writeable(obj));
218-
spi->DR = (uint8_t)value;
254+
if(obj->bits == SPI_DATASIZE_8BIT)
255+
spi->DR = (uint8_t)value; // 8 bit mode
256+
else spi->DR = (uint16_t)value; // 16 bit mode
219257
}
220258

221259
static inline int ssp_read(spi_t *obj) {

0 commit comments

Comments
 (0)