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Merge pull request #10619 from jamesbeyond/fm-iap
Fastmodel: enable flashIAP and kvstore
2 parents 3ef8d1b + 81c96a7 commit 149d53c

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27 files changed

+139
-167
lines changed

27 files changed

+139
-167
lines changed

‎components/storage/blockdevice/COMPONENT_FLASHIAP/mbed_lib.json

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -14,6 +14,10 @@
1414
"REALTEK_RTL8195AM": {
1515
"base-address": "0x1C0000",
1616
"size": "0x40000"
17+
},
18+
"FVP_MPS2": {
19+
"base-address": "0x00200000",
20+
"size": "0x200000"
1721
}
1822
}
1923
}

‎features/storage/TESTS/kvstore/filesystemstore_tests/main.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -27,8 +27,8 @@
2727
#include "utest.h"
2828
#include <stdlib.h>
2929

30-
#if !defined(TARGET_K64F)
31-
#error [NOT_SUPPORTED] Kvstore API tests run only on K64F devices
30+
#if !defined(TARGET_K64F) && !defined(TARGET_ARM_FM)
31+
#error [NOT_SUPPORTED] Kvstore API tests run only on K64F devices and Fastmodels
3232
#endif
3333

3434
#define FSST_TEST_NUM_OF_THREADS 5

‎features/storage/TESTS/kvstore/general_tests_phase_1/main.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -29,8 +29,8 @@
2929
using namespace utest::v1;
3030
using namespace mbed;
3131

32-
#if !defined(TARGET_K64F)
33-
#error [NOT_SUPPORTED] Kvstore API tests run only on K64F devices
32+
#if !defined(TARGET_K64F) && !defined(TARGET_ARM_FM)
33+
#error [NOT_SUPPORTED] Kvstore API tests run only on K64F devices and Fastmodels
3434
#endif
3535

3636
static const char data[] = "data";

‎features/storage/TESTS/kvstore/general_tests_phase_2/main.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -29,8 +29,8 @@
2929
using namespace utest::v1;
3030
using namespace mbed;
3131

32-
#if !defined(TARGET_K64F)
33-
#error [NOT_SUPPORTED] Kvstore API tests run only on K64F devices
32+
#if !defined(TARGET_K64F) && !defined(TARGET_ARM_FM)
33+
#error [NOT_SUPPORTED] Kvstore API tests run only on K64F devices and Fastmodels
3434
#endif
3535

3636
static const char data[] = "data";

‎features/storage/TESTS/kvstore/securestore_whitebox/main.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -34,8 +34,8 @@
3434
#include <stdio.h>
3535
#include <algorithm>
3636

37-
#if !defined(TARGET_K64F)
38-
#error [NOT_SUPPORTED] Kvstore API tests run only on K64F devices
37+
#if !defined(TARGET_K64F) && !defined(TARGET_ARM_FM)
38+
#error [NOT_SUPPORTED] Kvstore API tests run only on K64F devices and Fastmodels
3939
#endif
4040

4141
#if !SECURESTORE_ENABLED

‎features/storage/kvstore/conf/tdb_internal/mbed_lib.json

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Original file line numberDiff line numberDiff line change
@@ -22,6 +22,10 @@
2222
"ARM_MUSCA_A1_S": {
2323
"internal_size": "0x8000",
2424
"internal_base_address": "0x00420000"
25+
},
26+
"FVP_MPS2": {
27+
"internal_size": "0x200000",
28+
"internal_base_address": "0x00200000"
2529
}
2630
}
2731
}

‎targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0/device/TOOLCHAIN_ARM_STD/MPS2.sct

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,9 @@
11
#! armcc -E
22
;* MPS2 CMSIS Library
33
;*
4-
;* Copyright (c) 2006-2018 ARM Limited
4+
;* Copyright (c) 2006-2019 ARM Limited
55
;* All rights reserved.
6+
;* SPDX-License-Identifier: Apache-2.0
67
;*
78
;* Redistribution and use in source and binary forms, with or without
89
;* modification, are permitted provided that the following conditions are met:
@@ -37,26 +38,25 @@
3738
#include "../memory_zones.h"
3839
#include "../cmsis_nvic.h"
3940

41+
#if !defined(MBED_BOOT_STACK_SIZE)
42+
#define MBED_BOOT_STACK_SIZE 0x400
43+
#endif
44+
4045
#if (defined(__stack_size__))
4146
#define STACK_SIZE __stack_size__
4247
#else
43-
#define STACK_SIZE 0x0400
48+
#define STACK_SIZE MBED_BOOT_STACK_SIZE
4449
#endif
4550

4651
; The vector table is loaded at address 0x00000000 in Flash memory region.
47-
LR_IROM1 MAPPABLE_START MAPPABLE_SIZE {
48-
ER_IROM1 MAPPABLE_START MAPPABLE_SIZE {
52+
LR_IROM1 ZBT_SRAM1_START ZBT_SRAM1_SIZE { ; load region size_region
53+
ER_IROM1 ZBT_SRAM1_START ZBT_SRAM1_SIZE { ; load address = execution address
4954
*.o (RESET, +First)
50-
}
51-
}
52-
53-
LR_IROM2 ZBT_SRAM1_START ZBT_SRAM1_SIZE { ; load region size_region
54-
ER_IROM2 ZBT_SRAM1_START ZBT_SRAM1_SIZE { ; load address = execution address
5555
*(InRoot$$Sections)
5656
*(+RO)
5757
}
5858
; NVIC_VECTORS_SIZE Total: 64 vectors = 256 bytes (0x100) to be reserved in RAM
59-
RW_IRAM1 (ZBT_SRAM2_START + NVIC_VECTORS_SIZE) (ZBT_SRAM2_SIZE - NVIC_VECTORS_SIZE) { ; RW data
59+
RW_IRAM1 (ZBT_SRAM2_START + NVIC_VECTORS_SIZE) (ZBT_SRAM2_SIZE - NVIC_VECTORS_SIZE - STACK_SIZE) { ; RW data
6060
*(+RW +ZI)
6161
}
6262
ARM_LIB_STACK (ZBT_SRAM2_START + ZBT_SRAM2_SIZE) EMPTY - STACK_SIZE { ; Stack region growing down

‎targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0/device/TOOLCHAIN_GCC_ARM/MPS2.ld

Lines changed: 3 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,7 @@
22
* MPS2 CMSIS Library
33
*/
44
/*
5-
* Copyright (c) 2009-2018 ARM Limited. All rights reserved.
5+
* Copyright (c) 2009-2019 ARM Limited. All rights reserved.
66
*
77
* SPDX-License-Identifier: Apache-2.0
88
*
@@ -21,7 +21,7 @@
2121
/*
2222
* This file is derivative of CMSIS V5.00 gcc_arm.ld
2323
*/
24-
/* Linker script for mbed FVP Cortex-M0 on MPS2 */
24+
/* Linker script for mbed FVP Cortex-M on MPS2 */
2525

2626
/* Linker script to configure memory regions. */
2727
/* The length of the VECTORS region is a bit larger than
@@ -37,7 +37,6 @@
3737

3838
MEMORY
3939
{
40-
VECTORS (rx) : ORIGIN = MAPPABLE_START, LENGTH = MAPPABLE_SIZE
4140
FLASH (rx) : ORIGIN = ZBT_SRAM1_START, LENGTH = ZBT_SRAM1_SIZE
4241
RAM (rwx) : ORIGIN = ZBT_SRAM2_START, LENGTH = ZBT_SRAM2_SIZE
4342
}
@@ -82,7 +81,7 @@ SECTIONS
8281
__vector_table = .;
8382
KEEP(*(.vector_table))
8483
. = ALIGN(8);
85-
} > VECTORS
84+
} > FLASH
8685

8786
.text :
8887
{

‎targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0/device/TOOLCHAIN_IAR/MPS2.icf

Lines changed: 5 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,7 @@
22
* MPS2 CMSIS Library
33
*/
44
/*
5-
* Copyright (c) 2009-2018 ARM Limited. All rights reserved.
5+
* Copyright (c) 2009-2019 ARM Limited. All rights reserved.
66
*
77
* SPDX-License-Identifier: Apache-2.0
88
*
@@ -24,21 +24,19 @@
2424
* can not be included here. Please make sure that the two definitions match.
2525
*/
2626
/* Code memory zones */
27-
define symbol MAPPABLE_START = 0x00000000;
28-
define symbol MAPPABLE_SIZE = 0x00004000; /* 16 KiB */
29-
define symbol ZBT_SRAM1_START = (0x00000000 + 0x00004000);
30-
define symbol ZBT_SRAM1_SIZE = (0x00400000 - 0x00004000); /* 4 MiB - 16 KiB */
27+
define symbol ZBT_SRAM1_START = 0x00000000;
28+
define symbol ZBT_SRAM1_SIZE = 0x00400000; /* 4 MiB */
3129

3230
/* Data memory zones */
3331
define symbol ZBT_SRAM2_START = 0x20000000;
34-
define symbol ZBT_SRAM2_SIZE = 0x00400000; /* 4 MB */
32+
define symbol ZBT_SRAM2_SIZE = 0x00400000; /* 4 MiB */
3533

3634
/* NVIC vector numbers and size. */
3735
define symbol NVIC_NUM_VECTORS = (16 + 48);
3836
define symbol NVIC_VECTORS_SIZE = (NVIC_NUM_VECTORS * 4);
3937

4038
/*-Specials-*/
41-
define symbol __ICFEDIT_intvec_start__ = MAPPABLE_START;
39+
define symbol __ICFEDIT_intvec_start__ = ZBT_SRAM1_START;
4240

4341
/*-Memory Regions-*/
4442
define symbol __ICFEDIT_region_ROM_start__ = ZBT_SRAM1_START;

‎targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0/device/memory_zones.h

Lines changed: 4 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,6 @@
11
/*
2-
* Copyright (c) 2017-2018 ARM Limited
2+
* Copyright (c) 2017-2019 ARM Limited
3+
* SPDX-License-Identifier: Apache-2.0
34
*
45
* Licensed under the Apache License Version 2.0 (the "License");
56
* you may not use this file except in compliance with the License.
@@ -37,10 +38,8 @@
3738
* only to keep the same name than in the CMSDK RTL and Fast Models Reference
3839
* Guide.
3940
*/
40-
#define MAPPABLE_START 0x00000000
41-
#define MAPPABLE_SIZE 0x00004000 /* 16 KiB */
42-
#define ZBT_SRAM1_START (0x00000000 + 0x00004000)
43-
#define ZBT_SRAM1_SIZE (0x00400000 - 0x00004000) /* 4 MiB - 16 KiB*/
41+
#define ZBT_SRAM1_START 0x00000000
42+
#define ZBT_SRAM1_SIZE 0x00400000 /* 4 MiB */
4443

4544
/* Data memory zones */
4645
#define ZBT_SRAM2_START 0x20000000

‎targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0P/device/TOOLCHAIN_ARM_STD/MPS2.sct

Lines changed: 4 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,9 @@
11
#! armcc -E
22
;* MPS2 CMSIS Library
33
;*
4-
;* Copyright (c) 2006-2018 ARM Limited
4+
;* Copyright (c) 2006-2019 ARM Limited
55
;* All rights reserved.
6+
;* SPDX-License-Identifier: Apache-2.0
67
;*
78
;* Redistribution and use in source and binary forms, with or without
89
;* modification, are permitted provided that the following conditions are met:
@@ -48,14 +49,9 @@
4849
#endif
4950

5051
; The vector table is loaded at address 0x00000000 in Flash memory region.
51-
LR_IROM1 MAPPABLE_START MAPPABLE_SIZE {
52-
ER_IROM1 MAPPABLE_START MAPPABLE_SIZE {
52+
LR_IROM1 ZBT_SRAM1_START ZBT_SRAM1_SIZE { ; load region size_region
53+
ER_IROM1 ZBT_SRAM1_START ZBT_SRAM1_SIZE { ; load address = execution address
5354
*.o (RESET, +First)
54-
}
55-
}
56-
57-
LR_IROM2 ZBT_SRAM1_START ZBT_SRAM1_SIZE { ; load region size_region
58-
ER_IROM2 ZBT_SRAM1_START ZBT_SRAM1_SIZE { ; load address = execution address
5955
*(InRoot$$Sections)
6056
*(+RO)
6157
}

‎targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0P/device/TOOLCHAIN_GCC_ARM/MPS2.ld

Lines changed: 7 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,7 @@
22
* MPS2 CMSIS Library
33
*/
44
/*
5-
* Copyright (c) 2009-2018 ARM Limited. All rights reserved.
5+
* Copyright (c) 2009-2019 ARM Limited. All rights reserved.
66
*
77
* SPDX-License-Identifier: Apache-2.0
88
*
@@ -21,7 +21,7 @@
2121
/*
2222
* This file is derivative of CMSIS V5.00 gcc_arm.ld
2323
*/
24-
/* Linker script for mbed FVP Cortex-M0-Plus on MPS2 */
24+
/* Linker script for mbed FVP Cortex-M on MPS2 */
2525

2626
/* Linker script to configure memory regions. */
2727
/* The length of the VECTORS region is a bit larger than
@@ -31,9 +31,12 @@
3131
#include "../memory_zones.h"
3232
#include "../cmsis_nvic.h"
3333

34+
#if !defined(MBED_BOOT_STACK_SIZE)
35+
#define MBED_BOOT_STACK_SIZE 0x400
36+
#endif
37+
3438
MEMORY
3539
{
36-
VECTORS (rx) : ORIGIN = MAPPABLE_START, LENGTH = MAPPABLE_SIZE
3740
FLASH (rx) : ORIGIN = ZBT_SRAM1_START, LENGTH = ZBT_SRAM1_SIZE
3841
RAM (rwx) : ORIGIN = ZBT_SRAM2_START, LENGTH = ZBT_SRAM2_SIZE
3942
}
@@ -66,10 +69,6 @@ MEMORY
6669
*/
6770
ENTRY(Reset_Handler)
6871

69-
#if !defined(MBED_BOOT_STACK_SIZE)
70-
#define MBED_BOOT_STACK_SIZE 0x400
71-
#endif
72-
7372
STACK_SIZE = MBED_BOOT_STACK_SIZE;
7473

7574
/* Size of the vector table in SRAM */
@@ -82,7 +81,7 @@ SECTIONS
8281
__vector_table = .;
8382
KEEP(*(.vector_table))
8483
. = ALIGN(8);
85-
} > VECTORS
84+
} > FLASH
8685

8786
.text :
8887
{

‎targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0P/device/TOOLCHAIN_IAR/MPS2.icf

Lines changed: 5 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,7 @@
22
* MPS2 CMSIS Library
33
*/
44
/*
5-
* Copyright (c) 2009-2018 ARM Limited. All rights reserved.
5+
* Copyright (c) 2009-2019 ARM Limited. All rights reserved.
66
*
77
* SPDX-License-Identifier: Apache-2.0
88
*
@@ -24,21 +24,19 @@
2424
* can not be included here. Please make sure that the two definitions match.
2525
*/
2626
/* Code memory zones */
27-
define symbol MAPPABLE_START = 0x00000000;
28-
define symbol MAPPABLE_SIZE = 0x00004000; /* 16 KiB */
29-
define symbol ZBT_SRAM1_START = (0x00000000 + 0x00004000);
30-
define symbol ZBT_SRAM1_SIZE = (0x00400000 - 0x00004000); /* 4 MiB - 16 KiB */
27+
define symbol ZBT_SRAM1_START = 0x00000000;
28+
define symbol ZBT_SRAM1_SIZE = 0x00400000; /* 4 MiB */
3129

3230
/* Data memory zones */
3331
define symbol ZBT_SRAM2_START = 0x20000000;
34-
define symbol ZBT_SRAM2_SIZE = 0x00400000; /* 4 MB */
32+
define symbol ZBT_SRAM2_SIZE = 0x00400000; /* 4 MiB */
3533

3634
/* NVIC vector numbers and size. */
3735
define symbol NVIC_NUM_VECTORS = (16 + 48);
3836
define symbol NVIC_VECTORS_SIZE = (NVIC_NUM_VECTORS * 4);
3937

4038
/*-Specials-*/
41-
define symbol __ICFEDIT_intvec_start__ = MAPPABLE_START;
39+
define symbol __ICFEDIT_intvec_start__ = ZBT_SRAM1_START;
4240

4341
/*-Memory Regions-*/
4442
define symbol __ICFEDIT_region_ROM_start__ = ZBT_SRAM1_START;

‎targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0P/device/memory_zones.h

Lines changed: 4 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,6 @@
11
/*
2-
* Copyright (c) 2017-2018 ARM Limited
2+
* Copyright (c) 2017-2019 ARM Limited
3+
* SPDX-License-Identifier: Apache-2.0
34
*
45
* Licensed under the Apache License Version 2.0 (the "License");
56
* you may not use this file except in compliance with the License.
@@ -37,10 +38,8 @@
3738
* only to keep the same name than in the CMSDK RTL and Fast Models Reference
3839
* Guide.
3940
*/
40-
#define MAPPABLE_START 0x00000000
41-
#define MAPPABLE_SIZE 0x00004000 /* 16 KiB */
42-
#define ZBT_SRAM1_START (0x00000000 + 0x00004000)
43-
#define ZBT_SRAM1_SIZE (0x00400000 - 0x00004000) /* 4 MiB - 16 KiB*/
41+
#define ZBT_SRAM1_START 0x00000000
42+
#define ZBT_SRAM1_SIZE 0x00400000 /* 4 MiB */
4443

4544
/* Data memory zones */
4645
#define ZBT_SRAM2_START 0x20000000

‎targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M3/device/TOOLCHAIN_ARM_STD/MPS2.sct

Lines changed: 4 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,9 @@
11
#! armcc -E
22
;* MPS2 CMSIS Library
33
;*
4-
;* Copyright (c) 2006-2018 ARM Limited
4+
;* Copyright (c) 2006-2019 ARM Limited
55
;* All rights reserved.
6+
;* SPDX-License-Identifier: Apache-2.0
67
;*
78
;* Redistribution and use in source and binary forms, with or without
89
;* modification, are permitted provided that the following conditions are met:
@@ -48,14 +49,9 @@
4849
#endif
4950

5051
; The vector table is loaded at address 0x00000000 in Flash memory region.
51-
LR_IROM1 MAPPABLE_START MAPPABLE_SIZE {
52-
ER_IROM1 MAPPABLE_START MAPPABLE_SIZE {
52+
LR_IROM1 ZBT_SRAM1_START ZBT_SRAM1_SIZE { ; load region size_region
53+
ER_IROM1 ZBT_SRAM1_START ZBT_SRAM1_SIZE { ; load address = execution address
5354
*.o (RESET, +First)
54-
}
55-
}
56-
57-
LR_IROM2 ZBT_SRAM1_START ZBT_SRAM1_SIZE { ; load region size_region
58-
ER_IROM2 ZBT_SRAM1_START ZBT_SRAM1_SIZE { ; load address = execution address
5955
*(InRoot$$Sections)
6056
*(+RO)
6157
}

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