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RTC subSeconds at 16384Hz
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2 files changed

+30
-3
lines changed

2 files changed

+30
-3
lines changed

libraries/mbed/targets/hal/TARGET_STM/TARGET_MOTE_L152RC/rtc_api.c

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -86,8 +86,9 @@ void rtc_init(void)
8686
__HAL_RCC_RTC_ENABLE();
8787

8888
RtcHandle.Init.HourFormat = RTC_HOURFORMAT_24;
89-
RtcHandle.Init.AsynchPrediv = 127;
90-
RtcHandle.Init.SynchPrediv = (rtc_freq / 128) - 1;
89+
/* SubSecond resolution of 16384Hz */
90+
RtcHandle.Init.AsynchPrediv = /*127*/ 1;
91+
RtcHandle.Init.SynchPrediv = (rtc_freq / /*128*/ 2) - 1;
9192
RtcHandle.Init.OutPut = RTC_OUTPUT_DISABLE;
9293
RtcHandle.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH;
9394
RtcHandle.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN;

libraries/mbed/targets/hal/TARGET_STM/TARGET_MOTE_L152RC/sleep.c

100644100755
Lines changed: 27 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -50,12 +50,38 @@ void sleep(void)
5050

5151
void deepsleep(void)
5252
{
53+
uint8_t STOPEntry = PWR_STOPENTRY_WFI; /* PWR_STOPENTRY_WFE */
54+
5355
// Disable HAL tick interrupt
5456
TimMasterHandle.Instance = TIM5;
5557
__HAL_TIM_DISABLE_IT(&TimMasterHandle, TIM_IT_CC2);
5658

5759
// Request to enter STOP mode with regulator in low power mode
58-
HAL_PWR_EnterSTOPMode(PWR_LOWPOWERREGULATOR_ON, PWR_STOPENTRY_WFI);
60+
//HAL_PWR_EnterSTOPMode(PWR_LOWPOWERREGULATOR_ON, PWR_STOPENTRY_WFI);
61+
/* Select the regulator state in Stop mode: Set PDDS and LPSDSR bit according to PWR_Regulator value */
62+
MODIFY_REG(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPSDSR), PWR_LOWPOWERREGULATOR_ON);
63+
64+
/* Set SLEEPDEEP bit of Cortex System Control Register */
65+
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
66+
67+
/* Select Stop mode entry --------------------------------------------------*/
68+
if(STOPEntry == PWR_STOPENTRY_WFI)
69+
{
70+
/* Request Wait For Interrupt */
71+
__WFI();
72+
}
73+
else
74+
{
75+
/* Request Wait For Event */
76+
__SEV();
77+
__WFE();
78+
__WFE();
79+
}
80+
__NOP();
81+
__NOP();
82+
__NOP();
83+
/* Reset SLEEPDEEP bit of Cortex System Control Register */
84+
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
5985

6086
// After wake-up from STOP reconfigure the PLL
6187
SetSysClock();

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