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TomoYamanakaTomoYamanaka
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Support Flash iAP for GR-PEACH and GR-LYCHEE
The mainly changes is below: - Add flash_api.c - Add the definition of SPI multi I/O Bus controller that is used for flash access - Add "FLASH" as device feature - Add the macro regarding information of the incorporated Flash - Add the processing to expand code to RAM
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16 files changed

+1503
-10
lines changed

16 files changed

+1503
-10
lines changed

‎targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/TOOLCHAIN_ARM_STD/MBRZA1LU.sct

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -32,7 +32,10 @@ SFLASH __ROM_BASE __ROM_SIZE ; load region size_region
3232
RO_DATA +0
3333
{ * (+RO-DATA) } ; Application RO data (.constdata)
3434

35-
RW_DATA 0x20020000
35+
RAM_CODE 0x20020000
36+
{ * (RAM_CODE) } ; Application RAM_CODE
37+
38+
RW_DATA +0 ALIGN 0x4
3639
{ * (+RW) } ; Application RW data (.data)
3740

3841
RW_IRAM1 +0 ALIGN 0x10

‎targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/TOOLCHAIN_GCC_ARM/RZA1LU.ld

Lines changed: 21 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -105,6 +105,9 @@ SECTIONS
105105
LONG (__etext2)
106106
LONG (__nc_data_start)
107107
LONG (__nc_data_end - __nc_data_start)
108+
LONG (LOADADDR(.ram_code))
109+
LONG (ADDR(.ram_code))
110+
LONG (SIZEOF(.ram_code))
108111
__copy_table_end__ = .;
109112
} > SFLASH
110113

@@ -119,15 +122,31 @@ SECTIONS
119122
__zero_table_end__ = .;
120123
} > SFLASH
121124

122-
__etext = .;
123-
125+
.ram_code : ALIGN( 0x4 ) {
126+
__ram_code_load = .;
127+
__ram_code_start = LOADADDR(.ram_code) + ( __ram_code_load - ADDR(.ram_code) );
128+
129+
*(RAM_CODE)
130+
131+
*(RAM_CONST)
132+
133+
. = ALIGN( 0x4 );
134+
__ram_code_end = LOADADDR(.ram_code) + ( . - ADDR(.ram_code) );
135+
} > RAM AT > SFLASH
136+
137+
Load$$SEC_RAM_CODE$$Base = LOADADDR(.ram_code);
138+
Image$$SEC_RAM_CODE$$Base = ADDR(.ram_code);
139+
Load$$SEC_RAM_CODE$$Length = SIZEOF(.ram_code);
140+
124141
.ttb :
125142
{
126143
Image$$TTB$$ZI$$Base = .;
127144
. += 0x00004000;
128145
Image$$TTB$$ZI$$Limit = .;
129146
} > L_TTB
130147

148+
__etext = Load$$SEC_RAM_CODE$$Base + SIZEOF(.ram_code);
149+
131150
.data : AT (__etext)
132151
{
133152
Image$$RW_DATA$$Base = .;

‎targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/inc/iobitmasks/spibsc_iobitmask.h

Lines changed: 250 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,250 @@
1+
/*******************************************************************************
2+
* DISCLAIMER
3+
* This software is supplied by Renesas Electronics Corporation and is only
4+
* intended for use with Renesas products. No other uses are authorized. This
5+
* software is owned by Renesas Electronics Corporation and is protected under
6+
* all applicable laws, including copyright laws.
7+
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
8+
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
9+
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
10+
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
11+
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
12+
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
13+
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
14+
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
15+
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
16+
* Renesas reserves the right, without notice, to make changes to this software
17+
* and to discontinue the availability of this software. By using this software,
18+
* you agree to the additional terms and conditions found by accessing the
19+
* following link:
20+
* http://www.renesas.com/disclaimer
21+
*
22+
* Copyright (C) 2016 Renesas Electronics Corporation. All rights reserved.
23+
*******************************************************************************/
24+
/*******************************************************************************
25+
* File Name : spibsc_iobitmask.h
26+
* $Rev: 6 $
27+
* $Date:: 2016-05-10 12:25:41 +0900#$
28+
* Description : SPI multi I/O bus controller register define header(for RZ/A1LU)
29+
*******************************************************************************/
30+
#ifndef __SPIBSC_IOBITMASK_H__
31+
#define __SPIBSC_IOBITMASK_H__
32+
33+
34+
/* ==== Mask values for IO registers ==== */
35+
#define SPIBSC_CMNCR_BSZ (0x00000003uL)
36+
#define SPIBSC_CMNCR_CPOL (0x00000008uL)
37+
#define SPIBSC_CMNCR_SSLP (0x00000010uL)
38+
#define SPIBSC_CMNCR_CPHAR (0x00000020uL)
39+
#define SPIBSC_CMNCR_CPHAT (0x00000040uL)
40+
#define SPIBSC_CMNCR_IO0FV (0x00000300uL)
41+
#define SPIBSC_CMNCR_IO2FV (0x00003000uL)
42+
#define SPIBSC_CMNCR_IO3FV (0x0000C000uL)
43+
#define SPIBSC_CMNCR_MOIIO0 (0x00030000uL)
44+
#define SPIBSC_CMNCR_MOIIO1 (0x000C0000uL)
45+
#define SPIBSC_CMNCR_MOIIO2 (0x00300000uL)
46+
#define SPIBSC_CMNCR_MOIIO3 (0x00C00000uL)
47+
#define SPIBSC_CMNCR_SFDE (0x01000000uL)
48+
#define SPIBSC_CMNCR_MD (0x80000000uL)
49+
50+
#define SPIBSC_SSLDR_SCKDL (0x00000007uL)
51+
#define SPIBSC_SSLDR_SLNDL (0x00000700uL)
52+
#define SPIBSC_SSLDR_SPNDL (0x00070000uL)
53+
54+
#define SPIBSC_SPBCR_BRDV (0x00000003uL)
55+
#define SPIBSC_SPBCR_SPBR (0x0000FF00uL)
56+
57+
#define SPIBSC_DRCR_SSLE (0x00000001uL)
58+
#define SPIBSC_DRCR_RBE (0x00000100uL)
59+
#define SPIBSC_DRCR_RCF (0x00000200uL)
60+
#define SPIBSC_DRCR_RBURST (0x000F0000uL)
61+
#define SPIBSC_DRCR_SSLN (0x01000000uL)
62+
63+
#define SPIBSC_DRCMR_OCMD (0x000000FFuL)
64+
#define SPIBSC_DRCMR_CMD (0x00FF0000uL)
65+
66+
#define SPIBSC_DREAR_EAC (0x00000007uL)
67+
#define SPIBSC_DREAR_EAV (0x00FF0000uL)
68+
69+
#define SPIBSC_DROPR_OPD0 (0x000000FFuL)
70+
#define SPIBSC_DROPR_OPD1 (0x0000FF00uL)
71+
#define SPIBSC_DROPR_OPD2 (0x00FF0000uL)
72+
#define SPIBSC_DROPR_OPD3 (0xFF000000uL)
73+
74+
#define SPIBSC_DRENR_OPDE (0x000000F0uL)
75+
#define SPIBSC_DRENR_ADE (0x00000F00uL)
76+
#define SPIBSC_DRENR_OCDE (0x00001000uL)
77+
#define SPIBSC_DRENR_CDE (0x00004000uL)
78+
#define SPIBSC_DRENR_DME (0x00008000uL)
79+
#define SPIBSC_DRENR_DRDB (0x00030000uL)
80+
#define SPIBSC_DRENR_OPDB (0x00300000uL)
81+
#define SPIBSC_DRENR_ADB (0x03000000uL)
82+
#define SPIBSC_DRENR_OCDB (0x30000000uL)
83+
#define SPIBSC_DRENR_CDB (0xC0000000uL)
84+
85+
#define SPIBSC_SMCR_SPIE (0x00000001uL)
86+
#define SPIBSC_SMCR_SPIWE (0x00000002uL)
87+
#define SPIBSC_SMCR_SPIRE (0x00000004uL)
88+
#define SPIBSC_SMCR_SSLKP (0x00000100uL)
89+
90+
#define SPIBSC_SMCMR_OCMD (0x000000FFuL)
91+
#define SPIBSC_SMCMR_CMD (0x00FF0000uL)
92+
93+
#define SPIBSC_SMADR_ADR (0xFFFFFFFFuL)
94+
95+
#define SPIBSC_SMOPR_OPD0 (0x000000FFuL)
96+
#define SPIBSC_SMOPR_OPD1 (0x0000FF00uL)
97+
#define SPIBSC_SMOPR_OPD2 (0x00FF0000uL)
98+
#define SPIBSC_SMOPR_OPD3 (0xFF000000uL)
99+
100+
#define SPIBSC_SMENR_SPIDE (0x0000000FuL)
101+
#define SPIBSC_SMENR_OPDE (0x000000F0uL)
102+
#define SPIBSC_SMENR_ADE (0x00000F00uL)
103+
#define SPIBSC_SMENR_OCDE (0x00001000uL)
104+
#define SPIBSC_SMENR_CDE (0x00004000uL)
105+
#define SPIBSC_SMENR_DME (0x00008000uL)
106+
#define SPIBSC_SMENR_SPIDB (0x00030000uL)
107+
#define SPIBSC_SMENR_OPDB (0x00300000uL)
108+
#define SPIBSC_SMENR_ADB (0x03000000uL)
109+
#define SPIBSC_SMENR_OCDB (0x30000000uL)
110+
#define SPIBSC_SMENR_CDB (0xC0000000uL)
111+
112+
#define SPIBSC_SMRDR0_RDATA0 (0xFFFFFFFFuL)
113+
#define SPIBSC_SMRDR1_RDATA1 (0xFFFFFFFFuL)
114+
#define SPIBSC_SMWDR0_WDATA0 (0xFFFFFFFFuL)
115+
#define SPIBSC_SMWDR1_WDATA1 (0xFFFFFFFFuL)
116+
117+
#define SPIBSC_CMNSR_TEND (0x00000001uL)
118+
#define SPIBSC_CMNSR_SSLF (0x00000002uL)
119+
120+
#define SPIBSC_CKDLY_CKDLY (0x0000000fuL)
121+
#define SPIBSC_CKDLY_GB (0x00ff0000uL)
122+
123+
#define SPIBSC_DRDMCR_DMCYC (0x00000007uL)
124+
#define SPIBSC_DRDMCR_DMDB (0x00030000uL)
125+
126+
#define SPIBSC_DRDRENR_DRDRE (0x00000001uL)
127+
#define SPIBSC_DRDRENR_OPDRE (0x00000010uL)
128+
#define SPIBSC_DRDRENR_ADDRE (0x00000100uL)
129+
130+
#define SPIBSC_SMDMCR_DMCYC (0x00000007uL)
131+
#define SPIBSC_SMDMCR_DMDB (0x00030000uL)
132+
133+
#define SPIBSC_SMDRENR_SPIDRE (0x00000001uL)
134+
#define SPIBSC_SMDRENR_OPDRE (0x00000010uL)
135+
#define SPIBSC_SMDRENR_ADDRE (0x00000100uL)
136+
137+
#define SPIBSC_SPODLY_SPODLY (0x0000ffffuL)
138+
#define SPIBSC_SPODLY_GB (0xff000000uL)
139+
140+
/* Shift parameter */
141+
#define SPIBSC_CMNCR_BSZ_SHIFT (0u)
142+
#define SPIBSC_CMNCR_CPOL_SHIFT (3u)
143+
#define SPIBSC_CMNCR_SSLP_SHIFT (4u)
144+
#define SPIBSC_CMNCR_CPHAR_SHIFT (5u)
145+
#define SPIBSC_CMNCR_CPHAT_SHIFT (6u)
146+
#define SPIBSC_CMNCR_IO0FV_SHIFT (8u)
147+
#define SPIBSC_CMNCR_IO2FV_SHIFT (12u)
148+
#define SPIBSC_CMNCR_IO3FV_SHIFT (14u)
149+
#define SPIBSC_CMNCR_MOIIO0_SHIFT (16u)
150+
#define SPIBSC_CMNCR_MOIIO1_SHIFT (18u)
151+
#define SPIBSC_CMNCR_MOIIO2_SHIFT (20u)
152+
#define SPIBSC_CMNCR_MOIIO3_SHIFT (22u)
153+
#define SPIBSC_CMNCR_SFDE_SHIFT (24u)
154+
#define SPIBSC_CMNCR_MD_SHIFT (31u)
155+
156+
#define SPIBSC_SSLDR_SCKDL_SHIFT (0u)
157+
#define SPIBSC_SSLDR_SLNDL_SHIFT (8u)
158+
#define SPIBSC_SSLDR_SPNDL_SHIFT (16u)
159+
160+
#define SPIBSC_SPBCR_BRDV_SHIFT (0u)
161+
#define SPIBSC_SPBCR_SPBR_SHIFT (8u)
162+
163+
#define SPIBSC_DRCR_SSLE_SHIFT (0u)
164+
#define SPIBSC_DRCR_RBE_SHIFT (8u)
165+
#define SPIBSC_DRCR_RCF_SHIFT (9u)
166+
#define SPIBSC_DRCR_RBURST_SHIFT (16u)
167+
#define SPIBSC_DRCR_SSLN_SHIFT (24u)
168+
169+
#define SPIBSC_DRCMR_OCMD_SHIFT (0u)
170+
#define SPIBSC_DRCMR_CMD_SHIFT (16u)
171+
172+
#define SPIBSC_DREAR_EAC_SHIFT (0u)
173+
#define SPIBSC_DREAR_EAV_SHIFT (16u)
174+
175+
#define SPIBSC_DROPR_OPD0_SHIFT (0u)
176+
#define SPIBSC_DROPR_OPD1_SHIFT (8u)
177+
#define SPIBSC_DROPR_OPD2_SHIFT (16u)
178+
#define SPIBSC_DROPR_OPD3_SHIFT (24u)
179+
180+
#define SPIBSC_DRENR_OPDE_SHIFT (4u)
181+
#define SPIBSC_DRENR_ADE_SHIFT (8u)
182+
#define SPIBSC_DRENR_OCDE_SHIFT (12u)
183+
#define SPIBSC_DRENR_CDE_SHIFT (14u)
184+
#define SPIBSC_DRENR_DME_SHIFT (15u)
185+
#define SPIBSC_DRENR_DRDB_SHIFT (16u)
186+
#define SPIBSC_DRENR_OPDB_SHIFT (20u)
187+
#define SPIBSC_DRENR_ADB_SHIFT (24u)
188+
#define SPIBSC_DRENR_OCDB_SHIFT (28u)
189+
#define SPIBSC_DRENR_CDB_SHIFT (30u)
190+
191+
#define SPIBSC_SMCR_SPIE_SHIFT (0u)
192+
#define SPIBSC_SMCR_SPIWE_SHIFT (1u)
193+
#define SPIBSC_SMCR_SPIRE_SHIFT (2u)
194+
#define SPIBSC_SMCR_SSLKP_SHIFT (8u)
195+
196+
#define SPIBSC_SMCMR_OCMD_SHIFT (0u)
197+
#define SPIBSC_SMCMR_CMD_SHIFT (16u)
198+
199+
#define SPIBSC_SMADR_ADR_SHIFT (0u)
200+
201+
#define SPIBSC_SMOPR_OPD0_SHIFT (0u)
202+
#define SPIBSC_SMOPR_OPD1_SHIFT (8u)
203+
#define SPIBSC_SMOPR_OPD2_SHIFT (16u)
204+
#define SPIBSC_SMOPR_OPD3_SHIFT (24u)
205+
206+
#define SPIBSC_SMENR_SPIDE_SHIFT (0u)
207+
#define SPIBSC_SMENR_OPDE_SHIFT (4u)
208+
#define SPIBSC_SMENR_ADE_SHIFT (8u)
209+
#define SPIBSC_SMENR_OCDE_SHIFT (12u)
210+
#define SPIBSC_SMENR_CDE_SHIFT (14u)
211+
#define SPIBSC_SMENR_DME_SHIFT (15u)
212+
#define SPIBSC_SMENR_SPIDB_SHIFT (16u)
213+
#define SPIBSC_SMENR_OPDB_SHIFT (20u)
214+
#define SPIBSC_SMENR_ADB_SHIFT (24u)
215+
#define SPIBSC_SMENR_OCDB_SHIFT (28u)
216+
#define SPIBSC_SMENR_CDB_SHIFT (30u)
217+
218+
#define SPIBSC_SMRDR0_RDATA0_SHIFT (0u)
219+
#define SPIBSC_SMRDR1_RDATA1_SHIFT (0u)
220+
#define SPIBSC_SMWDR0_WDATA0_SHIFT (0u)
221+
#define SPIBSC_SMWDR1_WDATA1_SHIFT (0u)
222+
223+
#define SPIBSC_CMNSR_TEND_SHIFT (0u)
224+
#define SPIBSC_CMNSR_SSLF_SHIFT (1u)
225+
226+
#define SPIBSC_CKDLY_CKDLY_SHIFT (0u)
227+
#define SPIBSC_CKDLY_GB_SHIFT (8u)
228+
229+
#define SPIBSC_DRDMCR_DMCYC_SHIFT (0u)
230+
#define SPIBSC_DRDMCR_DMDB_SHIFT (16u)
231+
232+
#define SPIBSC_DRDRENR_DRDRE_SHIFT (0u)
233+
#define SPIBSC_DRDRENR_OPDRE_SHIFT (4u)
234+
#define SPIBSC_DRDRENR_ADDRE_SHIFT (8u)
235+
236+
#define SPIBSC_SMDMCR_DMCYC_SHIFT (0u)
237+
#define SPIBSC_SMDMCR_DMDB_SHIFT (16u)
238+
239+
#define SPIBSC_SMDRENR_SPIDRE_SHIFT (0u)
240+
#define SPIBSC_SMDRENR_OPDRE_SHIFT (4u)
241+
#define SPIBSC_SMDRENR_ADDRE_SHIFT (8u)
242+
243+
244+
#define SPIBSC_SPODLY_SPODLY_SHIFT (0u)
245+
#define SPIBSC_SPODLY_GB_SHIFT (24u)
246+
247+
248+
#endif /* __SPIBSC_IOBITMASK_H__ */
249+
250+
/* End of File */

‎targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/mmu_RZ_A1LU.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -204,7 +204,7 @@ void MMU_CreateTranslationTable(void)
204204
section_normal(Sect_Normal, region);
205205
section_normal_cod(Sect_Normal_Cod, region);
206206
section_normal_ro(Sect_Normal_RO, region);
207-
section_normal_rw(Sect_Normal_RW, region);
207+
section_normal(Sect_Normal_RW, region);
208208
//Create descriptors for peripherals
209209
section_device_ro(Sect_Device_RO, region);
210210
section_device_rw(Sect_Device_RW, region);

‎targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/system_RZ_A1LU.c

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -155,3 +155,9 @@ void SystemInit (void)
155155
// IRQ Initialize
156156
IRQ_Initialize();
157157
}
158+
159+
void mbed_sdk_init(void) {
160+
L1C_CleanDCacheAll();
161+
L1C_InvalidateICacheAll();
162+
}
163+

‎targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/mbed_drv_cfg.h

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -34,4 +34,10 @@
3434

3535
#define RENESAS_RZ_A1_P0_CLK CM1_RENESAS_RZ_A1_P0_CLK
3636

37+
/* flash (W25Q64JV) */
38+
#define FLASH_BASE (0x18000000UL) /**< Flash Base Address */
39+
#define FLASH_SIZE (0x00800000UL) /**< Available Flash Memory */
40+
#define FLASH_PAGE_SIZE 256 /**< Flash Memory page size (interleaving off) */
41+
#define FLASH_SECTOR_SIZE 4096 /**< Flash Memory sector size (interleaving off) */
42+
3743
#endif

‎targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/TOOLCHAIN_ARM_STD/MBRZA1H.sct

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -32,7 +32,10 @@ SFLASH __ROM_BASE __ROM_SIZE ; load region size_region
3232
RO_DATA +0
3333
{ * (+RO-DATA) } ; Application RO data (.constdata)
3434

35-
RW_DATA 0x20020000
35+
RAM_CODE 0x20020000
36+
{ * (RAM_CODE) } ; Application RAM_CODE
37+
38+
RW_DATA +0 ALIGN 0x4
3639
{ * (+RW) } ; Application RW data (.data)
3740

3841
RW_IRAM1 +0 ALIGN 0x10

‎targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/TOOLCHAIN_GCC_ARM/RZA1H.ld

Lines changed: 21 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -105,6 +105,9 @@ SECTIONS
105105
LONG (__etext2)
106106
LONG (__nc_data_start)
107107
LONG (__nc_data_end - __nc_data_start)
108+
LONG (LOADADDR(.ram_code))
109+
LONG (ADDR(.ram_code))
110+
LONG (SIZEOF(.ram_code))
108111
__copy_table_end__ = .;
109112
} > SFLASH
110113

@@ -119,15 +122,31 @@ SECTIONS
119122
__zero_table_end__ = .;
120123
} > SFLASH
121124

122-
__etext = .;
123-
125+
.ram_code : ALIGN( 0x4 ) {
126+
__ram_code_load = .;
127+
__ram_code_start = LOADADDR(.ram_code) + ( __ram_code_load - ADDR(.ram_code) );
128+
129+
*(RAM_CODE)
130+
131+
*(RAM_CONST)
132+
133+
. = ALIGN( 0x4 );
134+
__ram_code_end = LOADADDR(.ram_code) + ( . - ADDR(.ram_code) );
135+
} > RAM AT > SFLASH
136+
137+
Load$$SEC_RAM_CODE$$Base = LOADADDR(.ram_code);
138+
Image$$SEC_RAM_CODE$$Base = ADDR(.ram_code);
139+
Load$$SEC_RAM_CODE$$Length = SIZEOF(.ram_code);
140+
124141
.ttb :
125142
{
126143
Image$$TTB$$ZI$$Base = .;
127144
. += 0x00004000;
128145
Image$$TTB$$ZI$$Limit = .;
129146
} > L_TTB
130147

148+
__etext = Load$$SEC_RAM_CODE$$Base + SIZEOF(.ram_code);
149+
131150
.data : AT (__etext)
132151
{
133152
Image$$RW_DATA$$Base = .;

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