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Qinghao ShiQinghao Shi
Qinghao Shi
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Qinghao Shi
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FastModels: add FVP_MPS2_M0P target support
add cmsis drivers and toolchain scripts for FVP_MPS2_M0P
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‎targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0P/device/CMSDK_CM0plus.h

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‎targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0P/device/SMM_MPS2.h

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‎targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0P/device/TOOLCHAIN_ARM_STD/MPS2.sct

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;* MPS2 CMSIS Library
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;*
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;* Copyright (c) 2006-2018 ARM Limited
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;* All rights reserved.
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;*
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;* Redistribution and use in source and binary forms, with or without
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;* modification, are permitted provided that the following conditions are met:
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;*
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;* 1. Redistributions of source code must retain the above copyright notice,
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;* this list of conditions and the following disclaimer.
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;*
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;* 2. Redistributions in binary form must reproduce the above copyright notice,
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;* this list of conditions and the following disclaimer in the documentation
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;* and/or other materials provided with the distribution.
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;*
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;* 3. Neither the name of the copyright holder nor the names of its contributors
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;* may be used to endorse or promote products derived from this software without
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;* specific prior written permission.
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;*
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;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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;* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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;* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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;* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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;* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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;* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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;* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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;* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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;* POSSIBILITY OF SUCH DAMAGE.
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;*
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; *************************************************************
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; *** Scatter-Loading Description File ***
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; *************************************************************
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LR_IROM1 0x00000000 0x00400000 { ; load region size_region
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ER_IROM1 0x00000000 0x00400000 { ; load address = execution address
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*.o (RESET, +First)
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*(InRoot$$Sections)
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.ANY (+RO)
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}
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; Total: 64 vectors = 256 bytes (0x100) to be reserved in RAM
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RW_IRAM1 (0x20000000+0x100) (0x400000-0x100) { ; RW data
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.ANY (+RW +ZI)
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}
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}
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‎targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0P/device/TOOLCHAIN_ARM_STD/startup_MPS2.S

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; MPS2 CMSIS Library
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;
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; Copyright (c) 2006-2018 ARM Limited
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; All rights reserved.
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;
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; Redistribution and use in source and binary forms, with or without
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; modification, are permitted provided that the following conditions are met:
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;
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; 1. Redistributions of source code must retain the above copyright notice,
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; this list of conditions and the following disclaimer.
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;
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; 2. Redistributions in binary form must reproduce the above copyright notice,
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; this list of conditions and the following disclaimer in the documentation
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; and/or other materials provided with the distribution.
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;
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; 3. Neither the name of the copyright holder nor the names of its contributors
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; may be used to endorse or promote products derived from this software without
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; specific prior written permission.
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;
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; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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; POSSIBILITY OF SUCH DAMAGE.
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;******************************************************************************
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; @file startup_CMSDK_CM0P.s
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; @brief CMSIS Core Device Startup File for
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; CMSDK_CM0P Device
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;
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;******************************************************************************
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;
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;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
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;
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; <h> Stack Configuration
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; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
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; </h>
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Stack_Size EQU 0x00004000
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AREA STACK, NOINIT, READWRITE, ALIGN=3
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Stack_Mem SPACE Stack_Size
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__initial_sp
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; <h> Heap Configuration
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; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
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; </h>
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Heap_Size EQU 0x00001000
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AREA HEAP, NOINIT, READWRITE, ALIGN=3
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__heap_base
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Heap_Mem SPACE Heap_Size
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__heap_limit
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PRESERVE8
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THUMB
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; Vector Table Mapped to Address 0 at Reset
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AREA RESET, DATA, READONLY
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EXPORT __Vectors
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EXPORT __Vectors_End
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EXPORT __Vectors_Size
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__Vectors DCD __initial_sp ; Top of Stack
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DCD Reset_Handler ; Reset Handler
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DCD NMI_Handler ; NMI Handler
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DCD HardFault_Handler ; Hard Fault Handler
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD SVC_Handler ; SVCall Handler
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD PendSV_Handler ; PendSV Handler
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DCD SysTick_Handler ; SysTick Handler
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; External Interrupts
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DCD UARTRX0_Handler ; UART 0 RX Handler
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DCD UARTTX0_Handler ; UART 0 TX Handler
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DCD UARTRX1_Handler ; UART 1 RX Handler
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DCD UARTTX1_Handler ; UART 1 TX Handler
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DCD UARTRX2_Handler ; UART 2 RX Handler
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DCD UARTTX2_Handler ; UART 2 TX Handler
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DCD PORT0_COMB_Handler ; GPIO Port 0 Combined Handler
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DCD PORT1_COMB_Handler ; GPIO Port 1 Combined Handler
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DCD TIMER0_Handler ; TIMER 0 handler
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DCD TIMER1_Handler ; TIMER 1 handler
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DCD DUALTIMER_HANDLER ; Dual timer handler
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DCD SPI_Handler ; SPI exceptions Handler
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DCD UARTOVF_Handler ; UART 0,1,2 Overflow Handler
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DCD ETHERNET_Handler ; Ethernet Overflow Handler
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DCD I2S_Handler ; I2S Handler
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DCD TSC_Handler ; Touch Screen handler
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DCD PORT2_COMB_Handler ; GPIO Port 2 Combined Handler
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DCD PORT3_COMB_Handler ; GPIO Port 3 Combined Handler
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DCD UARTRX3_Handler ; UART 3 RX Handler
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DCD UARTTX3_Handler ; UART 3 TX Handler
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DCD UARTRX4_Handler ; UART 4 RX Handler
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DCD UARTTX4_Handler ; UART 4 TX Handler
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DCD ADCSPI_Handler ; SHIELD ADC SPI exceptions Handler
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DCD SHIELDSPI_Handler ; SHIELD SPI exceptions Handler
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DCD PORT0_0_Handler ; GPIO Port 0 pin 0 Handler
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DCD PORT0_1_Handler ; GPIO Port 0 pin 1 Handler
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DCD PORT0_2_Handler ; GPIO Port 0 pin 2 Handler
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DCD PORT0_3_Handler ; GPIO Port 0 pin 3 Handler
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DCD PORT0_4_Handler ; GPIO Port 0 pin 4 Handler
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DCD PORT0_5_Handler ; GPIO Port 0 pin 5 Handler
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DCD PORT0_6_Handler ; GPIO Port 0 pin 6 Handler
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DCD PORT0_7_Handler ; GPIO Port 0 pin 7 Handler
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__Vectors_End
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__Vectors_Size EQU __Vectors_End - __Vectors
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AREA |.text|, CODE, READONLY
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; Reset Handler
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Reset_Handler PROC
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EXPORT Reset_Handler [WEAK]
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IMPORT SystemInit
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IMPORT __main
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LDR R0, =SystemInit
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BLX R0
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LDR R0, =__main
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BX R0
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ENDP
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; Dummy Exception Handlers (infinite loops which can be modified)
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NMI_Handler PROC
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EXPORT NMI_Handler [WEAK]
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B .
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ENDP
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HardFault_Handler\
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PROC
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EXPORT HardFault_Handler [WEAK]
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B .
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ENDP
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SVC_Handler PROC
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EXPORT SVC_Handler [WEAK]
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B .
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ENDP
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PendSV_Handler PROC
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EXPORT PendSV_Handler [WEAK]
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B .
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ENDP
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SysTick_Handler PROC
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EXPORT SysTick_Handler [WEAK]
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B .
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ENDP
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Default_Handler PROC
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EXPORT UARTRX0_Handler [WEAK]
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EXPORT UARTTX0_Handler [WEAK]
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EXPORT UARTRX1_Handler [WEAK]
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EXPORT UARTTX1_Handler [WEAK]
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EXPORT UARTRX2_Handler [WEAK]
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EXPORT UARTTX2_Handler [WEAK]
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EXPORT PORT0_COMB_Handler [WEAK]
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EXPORT PORT1_COMB_Handler [WEAK]
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EXPORT TIMER0_Handler [WEAK]
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EXPORT TIMER1_Handler [WEAK]
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EXPORT DUALTIMER_HANDLER [WEAK]
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EXPORT SPI_Handler [WEAK]
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EXPORT UARTOVF_Handler [WEAK]
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EXPORT ETHERNET_Handler [WEAK]
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EXPORT I2S_Handler [WEAK]
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EXPORT TSC_Handler [WEAK]
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EXPORT PORT2_COMB_Handler [WEAK]
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EXPORT PORT3_COMB_Handler [WEAK]
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EXPORT UARTRX3_Handler [WEAK]
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EXPORT UARTTX3_Handler [WEAK]
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EXPORT UARTRX4_Handler [WEAK]
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EXPORT UARTTX4_Handler [WEAK]
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EXPORT ADCSPI_Handler [WEAK]
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EXPORT SHIELDSPI_Handler [WEAK]
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EXPORT PORT0_0_Handler [WEAK]
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EXPORT PORT0_1_Handler [WEAK]
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EXPORT PORT0_2_Handler [WEAK]
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EXPORT PORT0_3_Handler [WEAK]
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EXPORT PORT0_4_Handler [WEAK]
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EXPORT PORT0_5_Handler [WEAK]
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EXPORT PORT0_6_Handler [WEAK]
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EXPORT PORT0_7_Handler [WEAK]
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UARTRX0_Handler
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UARTTX0_Handler
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UARTRX1_Handler
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UARTTX1_Handler
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UARTRX2_Handler
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UARTTX2_Handler
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PORT0_COMB_Handler
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PORT1_COMB_Handler
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TIMER0_Handler
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TIMER1_Handler
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DUALTIMER_HANDLER
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SPI_Handler
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UARTOVF_Handler
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ETHERNET_Handler
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I2S_Handler
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TSC_Handler
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PORT2_COMB_Handler
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PORT3_COMB_Handler
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UARTRX3_Handler
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UARTTX3_Handler
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UARTRX4_Handler
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UARTTX4_Handler
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ADCSPI_Handler
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SHIELDSPI_Handler
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PORT0_0_Handler
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PORT0_1_Handler
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PORT0_2_Handler
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PORT0_3_Handler
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PORT0_4_Handler
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PORT0_5_Handler
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PORT0_6_Handler
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PORT0_7_Handler
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B .
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ENDP
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ALIGN
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; User Initial Stack & Heap
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IF :DEF:__MICROLIB
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EXPORT __initial_sp
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EXPORT __heap_base
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EXPORT __heap_limit
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ELSE
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IMPORT __use_two_region_memory
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EXPORT __user_initial_stackheap
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__user_initial_stackheap PROC
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LDR R0, = Heap_Mem
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LDR R1, =(Stack_Mem + Stack_Size)
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LDR R2, = (Heap_Mem + Heap_Size)
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LDR R3, = Stack_Mem
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BX LR
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ENDP
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ALIGN
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ENDIF
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END

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