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nvlsianpunvlsianpu
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nRF52 - switch irq priorities of driver handlers to level (APP_IRQ_PRIORITY_LOWEST) 7.
This is fix for bad settings inherited from nRF5 SDK. It might caused eroneus behavior when nrf_drv API were called form irq context etc.
1 parent 8f492a2 commit 1ca0918

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10 files changed

+69
-40
lines changed

10 files changed

+69
-40
lines changed

‎targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/analogin_api.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -35,7 +35,7 @@ static const nrf_drv_saadc_config_t saadc_config =
3535
{
3636
.resolution = NRF_SAADC_RESOLUTION_12BIT,
3737
.oversample = NRF_SAADC_OVERSAMPLE_DISABLED,
38-
.interrupt_priority = APP_IRQ_PRIORITY_LOW
38+
.interrupt_priority = SAADC_CONFIG_IRQ_PRIORITY
3939
};
4040

4141
void analogin_init(analogin_t *obj, PinName pin)

‎targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/pwmout_api.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -346,7 +346,7 @@ static void internal_pwmout_exe(pwmout_t *obj, bool new_period, bool initializat
346346
NRF_DRV_PWM_PIN_NOT_USED, // channel 2
347347
NRF_DRV_PWM_PIN_NOT_USED, // channel 3
348348
},
349-
.irq_priority = APP_IRQ_PRIORITY_LOW,
349+
.irq_priority = PWM0_CONFIG_IRQ_PRIORITY,
350350
.base_clock = pulsewidth_set.pwm_clk,
351351
.count_mode = NRF_PWM_MODE_UP,
352352
.top_value = pulsewidth_set.period_hwu,

‎targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/sdk/nrf_drv_config.h

Lines changed: 30 additions & 30 deletions
Original file line numberDiff line numberDiff line change
@@ -59,15 +59,15 @@
5959
#if (CLOCK_ENABLED == 1)
6060
#define CLOCK_CONFIG_XTAL_FREQ NRF_CLOCK_XTALFREQ_Default
6161
#define CLOCK_CONFIG_LF_SRC NRF_CLOCK_LFCLK_Xtal
62-
#define CLOCK_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
62+
#define CLOCK_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOWEST
6363
#endif
6464

6565
/* GPIOTE */
6666
#define GPIOTE_ENABLED 1
6767

6868
#if (GPIOTE_ENABLED == 1)
6969
#define GPIOTE_CONFIG_USE_SWI_EGU false
70-
#define GPIOTE_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
70+
#define GPIOTE_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOWEST
7171
#define GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS 8
7272
#endif
7373

@@ -82,7 +82,7 @@
8282
#define TIMER0_CONFIG_FREQUENCY NRF_TIMER_FREQ_16MHz
8383
#define TIMER0_CONFIG_MODE TIMER_MODE_MODE_Timer
8484
#define TIMER0_CONFIG_BIT_WIDTH TIMER_BITMODE_BITMODE_32Bit
85-
#define TIMER0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
85+
#define TIMER0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOWEST
8686

8787
#define TIMER0_INSTANCE_INDEX 0
8888
#endif
@@ -93,7 +93,7 @@
9393
#define TIMER1_CONFIG_FREQUENCY NRF_TIMER_FREQ_16MHz
9494
#define TIMER1_CONFIG_MODE TIMER_MODE_MODE_Timer
9595
#define TIMER1_CONFIG_BIT_WIDTH TIMER_BITMODE_BITMODE_16Bit
96-
#define TIMER1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
96+
#define TIMER1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOWEST
9797

9898
#define TIMER1_INSTANCE_INDEX (TIMER0_ENABLED)
9999
#endif
@@ -104,7 +104,7 @@
104104
#define TIMER2_CONFIG_FREQUENCY NRF_TIMER_FREQ_16MHz
105105
#define TIMER2_CONFIG_MODE TIMER_MODE_MODE_Timer
106106
#define TIMER2_CONFIG_BIT_WIDTH TIMER_BITMODE_BITMODE_16Bit
107-
#define TIMER2_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
107+
#define TIMER2_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOWEST
108108

109109
#define TIMER2_INSTANCE_INDEX (TIMER1_ENABLED+TIMER0_ENABLED)
110110
#endif
@@ -115,7 +115,7 @@
115115
#define TIMER3_CONFIG_FREQUENCY NRF_TIMER_FREQ_16MHz
116116
#define TIMER3_CONFIG_MODE TIMER_MODE_MODE_Timer
117117
#define TIMER3_CONFIG_BIT_WIDTH TIMER_BITMODE_BITMODE_16Bit
118-
#define TIMER3_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
118+
#define TIMER3_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOWEST
119119

120120
#define TIMER3_INSTANCE_INDEX (TIMER2_ENABLED+TIMER1_ENABLED+TIMER0_ENABLED)
121121
#endif
@@ -126,7 +126,7 @@
126126
#define TIMER4_CONFIG_FREQUENCY NRF_TIMER_FREQ_16MHz
127127
#define TIMER4_CONFIG_MODE TIMER_MODE_MODE_Timer
128128
#define TIMER4_CONFIG_BIT_WIDTH TIMER_BITMODE_BITMODE_16Bit
129-
#define TIMER4_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
129+
#define TIMER4_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOWEST
130130

131131
#define TIMER4_INSTANCE_INDEX (TIMER3_ENABLED+TIMER2_ENABLED+TIMER1_ENABLED+TIMER0_ENABLED)
132132
#endif
@@ -139,7 +139,7 @@
139139

140140
#if (RTC0_ENABLED == 1)
141141
#define RTC0_CONFIG_FREQUENCY 32678
142-
#define RTC0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
142+
#define RTC0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOWEST
143143
#define RTC0_CONFIG_RELIABLE false
144144

145145
#define RTC0_INSTANCE_INDEX 0
@@ -149,7 +149,7 @@
149149

150150
#if (RTC1_ENABLED == 1)
151151
#define RTC1_CONFIG_FREQUENCY 32768
152-
#define RTC1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
152+
#define RTC1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOWEST
153153
#define RTC1_CONFIG_RELIABLE false
154154

155155
#define RTC1_INSTANCE_INDEX (RTC0_ENABLED)
@@ -159,7 +159,7 @@
159159

160160
#if (RTC2_ENABLED == 1)
161161
#define RTC2_CONFIG_FREQUENCY 32768
162-
#define RTC2_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
162+
#define RTC2_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOWEST
163163
#define RTC2_CONFIG_RELIABLE false
164164

165165
#define RTC2_INSTANCE_INDEX (RTC0_ENABLED+RTC1_ENABLED)
@@ -176,7 +176,7 @@
176176
#if (RNG_ENABLED == 1)
177177
#define RNG_CONFIG_ERROR_CORRECTION true
178178
#define RNG_CONFIG_POOL_SIZE 8
179-
#define RNG_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
179+
#define RNG_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOWEST
180180
#endif
181181

182182
/* PWM */
@@ -188,7 +188,7 @@
188188
#define PWM0_CONFIG_OUT1_PIN 3
189189
#define PWM0_CONFIG_OUT2_PIN 4
190190
#define PWM0_CONFIG_OUT3_PIN 5
191-
#define PWM0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
191+
#define PWM0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOWEST
192192
#define PWM0_CONFIG_BASE_CLOCK NRF_PWM_CLK_1MHz
193193
#define PWM0_CONFIG_COUNT_MODE NRF_PWM_MODE_UP
194194
#define PWM0_CONFIG_TOP_VALUE 1000
@@ -205,7 +205,7 @@
205205
#define PWM1_CONFIG_OUT1_PIN 3
206206
#define PWM1_CONFIG_OUT2_PIN 4
207207
#define PWM1_CONFIG_OUT3_PIN 5
208-
#define PWM1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
208+
#define PWM1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOWEST
209209
#define PWM1_CONFIG_BASE_CLOCK NRF_PWM_CLK_1MHz
210210
#define PWM1_CONFIG_COUNT_MODE NRF_PWM_MODE_UP
211211
#define PWM1_CONFIG_TOP_VALUE 1000
@@ -222,7 +222,7 @@
222222
#define PWM2_CONFIG_OUT1_PIN 3
223223
#define PWM2_CONFIG_OUT2_PIN 4
224224
#define PWM2_CONFIG_OUT3_PIN 5
225-
#define PWM2_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
225+
#define PWM2_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOWEST
226226
#define PWM2_CONFIG_BASE_CLOCK NRF_PWM_CLK_1MHz
227227
#define PWM2_CONFIG_COUNT_MODE NRF_PWM_MODE_UP
228228
#define PWM2_CONFIG_TOP_VALUE 1000
@@ -243,7 +243,7 @@
243243
#define SPI0_CONFIG_SCK_PIN 2
244244
#define SPI0_CONFIG_MOSI_PIN 3
245245
#define SPI0_CONFIG_MISO_PIN 4
246-
#define SPI0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
246+
#define SPI0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOWEST
247247

248248
#define SPI0_INSTANCE_INDEX 0
249249
#endif
@@ -256,7 +256,7 @@
256256
#define SPI1_CONFIG_SCK_PIN 2
257257
#define SPI1_CONFIG_MOSI_PIN 3
258258
#define SPI1_CONFIG_MISO_PIN 4
259-
#define SPI1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
259+
#define SPI1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOWEST
260260

261261
#define SPI1_INSTANCE_INDEX (SPI0_ENABLED)
262262
#endif
@@ -269,7 +269,7 @@
269269
#define SPI2_CONFIG_SCK_PIN 2
270270
#define SPI2_CONFIG_MOSI_PIN 3
271271
#define SPI2_CONFIG_MISO_PIN 4
272-
#define SPI2_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
272+
#define SPI2_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOWEST
273273

274274
#define SPI2_INSTANCE_INDEX (SPI0_ENABLED + SPI1_ENABLED)
275275
#endif
@@ -283,7 +283,7 @@
283283
#define SPIS0_CONFIG_SCK_PIN 2
284284
#define SPIS0_CONFIG_MOSI_PIN 3
285285
#define SPIS0_CONFIG_MISO_PIN 4
286-
#define SPIS0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
286+
#define SPIS0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOWEST
287287

288288
#define SPIS0_INSTANCE_INDEX 0
289289
#endif
@@ -294,7 +294,7 @@
294294
#define SPIS1_CONFIG_SCK_PIN 2
295295
#define SPIS1_CONFIG_MOSI_PIN 3
296296
#define SPIS1_CONFIG_MISO_PIN 4
297-
#define SPIS1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
297+
#define SPIS1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOWEST
298298

299299
#define SPIS1_INSTANCE_INDEX SPIS0_ENABLED
300300
#endif
@@ -305,7 +305,7 @@
305305
#define SPIS2_CONFIG_SCK_PIN 2
306306
#define SPIS2_CONFIG_MOSI_PIN 3
307307
#define SPIS2_CONFIG_MISO_PIN 4
308-
#define SPIS2_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
308+
#define SPIS2_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOWEST
309309

310310
#define SPIS2_INSTANCE_INDEX (SPIS0_ENABLED + SPIS1_ENABLED)
311311
#endif
@@ -340,7 +340,7 @@
340340
#define TWI0_CONFIG_FREQUENCY NRF_TWI_FREQ_100K
341341
#define TWI0_CONFIG_SCL 0
342342
#define TWI0_CONFIG_SDA 1
343-
#define TWI0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
343+
#define TWI0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOWEST
344344

345345
#define TWI0_INSTANCE_INDEX 0
346346
#endif
@@ -353,7 +353,7 @@
353353
#define TWI1_CONFIG_FREQUENCY NRF_TWI_FREQ_100K
354354
#define TWI1_CONFIG_SCL 0
355355
#define TWI1_CONFIG_SDA 1
356-
#define TWI1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
356+
#define TWI1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOWEST
357357

358358
#define TWI1_INSTANCE_INDEX (TWI0_ENABLED)
359359
#endif
@@ -368,7 +368,7 @@
368368
#define TWIS0_CONFIG_ADDR1 0 /* 0: Disabled */
369369
#define TWIS0_CONFIG_SCL 0
370370
#define TWIS0_CONFIG_SDA 1
371-
#define TWIS0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
371+
#define TWIS0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOWEST
372372

373373
#define TWIS0_INSTANCE_INDEX 0
374374
#endif
@@ -380,7 +380,7 @@
380380
#define TWIS1_CONFIG_ADDR1 0 /* 0: Disabled */
381381
#define TWIS1_CONFIG_SCL 0
382382
#define TWIS1_CONFIG_SDA 1
383-
#define TWIS1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
383+
#define TWIS1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOWEST
384384

385385
#define TWIS1_INSTANCE_INDEX (TWIS0_ENABLED)
386386
#endif
@@ -402,7 +402,7 @@
402402
#define QDEC_CONFIG_PIO_LED 3
403403
#define QDEC_CONFIG_LEDPRE 511
404404
#define QDEC_CONFIG_LEDPOL NRF_QDEC_LEPOL_ACTIVE_HIGH
405-
#define QDEC_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
405+
#define QDEC_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOWEST
406406
#define QDEC_CONFIG_DBFEN false
407407
#define QDEC_CONFIG_SAMPLE_INTEN false
408408
#endif
@@ -411,7 +411,7 @@
411411
#define ADC_ENABLED 0
412412

413413
#if (ADC_ENABLED == 1)
414-
#define ADC_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
414+
#define ADC_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOWEST
415415
#endif
416416

417417

@@ -421,7 +421,7 @@
421421
#if (SAADC_ENABLED == 1)
422422
#define SAADC_CONFIG_RESOLUTION NRF_SAADC_RESOLUTION_10BIT
423423
#define SAADC_CONFIG_OVERSAMPLE NRF_SAADC_OVERSAMPLE_DISABLED
424-
#define SAADC_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
424+
#define SAADC_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOWEST
425425
#endif
426426

427427
/* PDM */
@@ -431,7 +431,7 @@
431431
#define PDM_CONFIG_MODE NRF_PDM_MODE_MONO
432432
#define PDM_CONFIG_EDGE NRF_PDM_EDGE_LEFTFALLING
433433
#define PDM_CONFIG_CLOCK_FREQ NRF_PDM_FREQ_1032K
434-
#define PDM_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
434+
#define PDM_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOWEST
435435
#endif
436436

437437
/* COMP */
@@ -443,7 +443,7 @@
443443
#define COMP_CONFIG_SPEED_MODE NRF_COMP_SP_MODE_High
444444
#define COMP_CONFIG_HYST NRF_COMP_HYST_NoHyst
445445
#define COMP_CONFIG_ISOURCE NRF_COMP_ISOURCE_Off
446-
#define COMP_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
446+
#define COMP_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOWEST
447447
#define COMP_CONFIG_INPUT NRF_COMP_INPUT_0
448448
#endif
449449

@@ -453,7 +453,7 @@
453453
#if (LPCOMP_ENABLED == 1)
454454
#define LPCOMP_CONFIG_REFERENCE NRF_LPCOMP_REF_SUPPLY_4_8
455455
#define LPCOMP_CONFIG_DETECTION NRF_LPCOMP_DETECT_DOWN
456-
#define LPCOMP_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
456+
#define LPCOMP_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOWEST
457457
#define LPCOMP_CONFIG_INPUT NRF_LPCOMP_INPUT_0
458458
#endif
459459

‎targets/TARGET_NORDIC/TARGET_NRF5/i2c_api.c

Lines changed: 7 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -124,8 +124,13 @@ void i2c_init(i2c_t *obj, PinName sda, PinName scl)
124124
nrf_drv_twi_config_t const config = {
125125
.scl = scl,
126126
.sda = sda,
127-
.frequency = NRF_TWI_FREQ_100K,
128-
.interrupt_priority = APP_IRQ_PRIORITY_LOW,
127+
.frequency = NRF_TWI_FREQ_100K,
128+
#ifdef NRF51
129+
.interrupt_priority = APP_IRQ_PRIORITY_LOW
130+
#elif defined(NRF52)
131+
.interrupt_priority = APP_IRQ_PRIORITY_LOWEST
132+
#endif
133+
129134
};
130135

131136
for (i = 0; i < TWI_COUNT; ++i) {

‎targets/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/common/nrf_drv_common.c

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -226,7 +226,11 @@ void nrf_drv_common_irq_enable(IRQn_Type IRQn, uint8_t priority)
226226
{
227227

228228
#ifdef SOFTDEVICE_PRESENT
229-
ASSERT((priority == APP_IRQ_PRIORITY_LOW) || (priority == APP_IRQ_PRIORITY_HIGH));
229+
#ifdef NRF51
230+
ASSERT((priority == APP_IRQ_PRIORITY_LOW) || (priority == APP_IRQ_PRIORITY_HIGH));
231+
#elif defined(NRF52)
232+
ASSERT((priority == APP_IRQ_PRIORITY_LOWEST) || (priority == APP_IRQ_PRIORITY_HIGH));
233+
#endif
230234
#endif
231235

232236
NVIC_SetPriority(IRQn, priority);

‎targets/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/pwm/app_pwm.c

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -789,7 +789,11 @@ ret_code_t app_pwm_init(app_pwm_t const * const p_instance, app_pwm_config_t con
789789
.frequency = timer_freq,
790790
.mode = NRF_TIMER_MODE_TIMER,
791791
.bit_width = NRF_TIMER_BIT_WIDTH_16,
792+
#ifdef NRF51
792793
.interrupt_priority = APP_IRQ_PRIORITY_LOW,
794+
#elif defined(NRF52)
795+
.interrupt_priority = APP_IRQ_PRIORITY_LOWEST,
796+
#endif
793797
.p_context = (void *) (uint32_t) p_instance->p_timer->instance_id
794798
};
795799
err_code = nrf_drv_timer_init(p_instance->p_timer, &timer_cfg,

‎targets/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/util/nrf_log.c

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -181,7 +181,11 @@ uint32_t log_uart_init()
181181
UART_RX_BUF_SIZE,
182182
UART_TX_BUF_SIZE,
183183
uart_error_cb,
184-
APP_IRQ_PRIORITY_LOW,
184+
#ifdef NRF51
185+
APP_IRQ_PRIORITY_LOW
186+
#elif defined(NRF52)
187+
APP_IRQ_PRIORITY_LOWEST
188+
#endif
185189
err_code);
186190

187191
initialized = true;

‎targets/TARGET_NORDIC/TARGET_NRF5/serial_api.c

Lines changed: 7 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -74,6 +74,12 @@
7474
#define UART_DEFAULT_CTS UART0_CONFIG_PSEL_CTS
7575
#define UART_DEFAULT_RTS UART0_CONFIG_PSEL_RTS
7676

77+
#ifdef NRF51
78+
#define NRFx_MBED_UART_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
79+
#elif defined(NRF52)
80+
#define NRFx_MBED_UART_IRQ_PRIORITY APP_IRQ_PRIORITY_LOWEST
81+
#endif
82+
7783
// Required by "retarget.cpp".
7884
int stdio_uart_inited = 0;
7985
serial_t stdio_uart;
@@ -287,7 +293,7 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) {
287293
#if DEVICE_SERIAL_ASYNCH
288294
nrf_uart_int_enable(UART_INSTANCE, NRF_UART_INT_MASK_ERROR);
289295
#endif
290-
nrf_drv_common_irq_enable(UART_IRQn, APP_IRQ_PRIORITY_LOW);
296+
nrf_drv_common_irq_enable(UART_IRQn, NRFx_MBED_UART_IRQ_PRIORITY);
291297

292298
// TX interrupt needs to be signaled when transmitter buffer is empty,
293299
// so a dummy transmission is needed to get the TXDRDY event initially

‎targets/TARGET_NORDIC/TARGET_NRF5/spi_api.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -201,7 +201,7 @@ static void prepare_master_config(nrf_drv_spi_config_t *p_config,
201201
p_config->frequency = p_spi_info->frequency;
202202
p_config->mode = (nrf_drv_spi_mode_t)p_spi_info->spi_mode;
203203

204-
p_config->irq_priority = APP_IRQ_PRIORITY_LOW;
204+
p_config->irq_priority = SPI1_CONFIG_IRQ_PRIORITY;
205205
p_config->orc = 0xFF;
206206
p_config->bit_order = NRF_DRV_SPI_BIT_ORDER_MSB_FIRST;
207207
}
@@ -215,7 +215,7 @@ static void prepare_slave_config(nrf_drv_spis_config_t *p_config,
215215
p_config->csn_pin = p_spi_info->ss_pin;
216216
p_config->mode = (nrf_drv_spis_mode_t)p_spi_info->spi_mode;
217217

218-
p_config->irq_priority = APP_IRQ_PRIORITY_LOW;
218+
p_config->irq_priority = SPIS1_CONFIG_IRQ_PRIORITY;
219219
p_config->orc = NRF_DRV_SPIS_DEFAULT_ORC;
220220
p_config->def = NRF_DRV_SPIS_DEFAULT_DEF;
221221
p_config->bit_order = NRF_DRV_SPIS_BIT_ORDER_MSB_FIRST;

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