Fix RAM size for LPC11C24 in ARM/uARM linker command files

Bogdan Marinescu · Bogdan Marinescu · commit 1e224c515266 · 2013-09-25T10:18:43.000+01:00
diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_ARM_MICRO/TARGET_LPC11CXX/LPC11C24.sct b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_ARM_MICRO/TARGET_LPC11CXX/LPC11C24.sct
@@ -0,0 +1,16 @@
+
+LR_IROM1 0x00000000 0x8000  {    ; load region size_region (32k)
+
+  ER_IROM1 0x00000000 0x8000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+
+  ; 48 vectors * 4 bytes = 0xC0 for remap
+  RW_IRAM1 (0x10000000+0xC0) (0x2000-0xC0)  {
+   .ANY (+RW +ZI)
+  }
+
+}
+
diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_ARM_STD/TARGET_LPC11CXX/LPC11C24.sct b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_ARM_STD/TARGET_LPC11CXX/LPC11C24.sct
@@ -0,0 +1,14 @@
+
+LR_IROM1 0x00000000 0x8000  {    ; load region size_region (32k)
+  ER_IROM1 0x00000000 0x8000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  ; 8_byte_aligned(48 vect * 4 bytes) =  8_byte_aligned(0xC0) = 0xC0
+  ; 8KB - 0xC0 = 0x1F40
+  RW_IRAM1 0x100000C0 0x1F40  {
+   .ANY (+RW +ZI)
+  }
+}
+
