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Merge pull request #14721 from OpenNuvoton/nuvoton_no-hxt-lxt
Nuvoton: Enable no HXT/LXT configurability
2 parents ae79b61 + f08a841 commit 1fe0650

32 files changed

+384
-99
lines changed

‎targets/TARGET_NUVOTON/TARGET_M251/device/system_M251.h

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -50,7 +50,11 @@ extern "C" {
5050
#define __HSI (48000000UL) /*!< PLL default output is 48MHz */
5151
#define __SYS_OSC_CLK ( ___HSI) /*!< Main oscillator frequency */
5252

53+
#if MBED_CONF_TARGET_HXT_PRESENT
5354
#define __SYSTEM_CLOCK (1UL*__HXT)
55+
#else
56+
#define __SYSTEM_CLOCK (1UL*__HIRC)
57+
#endif
5458

5559
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
5660
extern uint32_t CyclesPerUs; /*!< Cycles per micro second */

‎targets/TARGET_NUVOTON/TARGET_M251/lp_ticker.c

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -31,7 +31,11 @@
3131
/* Timer clock per lp_ticker tick */
3232
#define NU_TMRCLK_PER_TICK 1
3333
/* Timer clock per second */
34+
#if MBED_CONF_TARGET_LXT_PRESENT
3435
#define NU_TMRCLK_PER_SEC (__LXT)
36+
#else
37+
#define NU_TMRCLK_PER_SEC (__LIRC)
38+
#endif
3539
/* Timer max counter bit size */
3640
#define NU_TMR_MAXCNT_BITSIZE 24
3741
/* Timer max counter */
@@ -40,7 +44,11 @@
4044
static void tmr1_vec(void);
4145

4246
/* NOTE: To wake the system from power down mode, timer clock source must be ether LXT or LIRC. */
47+
#if MBED_CONF_TARGET_LXT_PRESENT
4348
static const struct nu_modinit_s timer1_modinit = {TIMER_1, TMR1_MODULE, CLK_CLKSEL1_TMR1SEL_LXT, 0, TMR1_RST, TMR1_IRQn, (void *) tmr1_vec};
49+
#else
50+
static const struct nu_modinit_s timer1_modinit = {TIMER_1, TMR1_MODULE, CLK_CLKSEL1_TMR1SEL_LIRC, 0, TMR1_RST, TMR1_IRQn, (void *) tmr1_vec};
51+
#endif
4452

4553
#define TIMER_MODINIT timer1_modinit
4654

‎targets/TARGET_NUVOTON/TARGET_M251/mbed_overrides.c

Lines changed: 20 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -33,47 +33,61 @@ void mbed_sdk_init(void)
3333
/* Unlock protected registers */
3434
SYS_UnlockReg();
3535

36-
#if defined(NU_HXT_ENABLE) && (NU_HXT_ENABLE == 1UL)
36+
#if MBED_CONF_TARGET_HXT_PRESENT
3737
/* HXT Enable: Set XT1_OUT(PF.2) and XT1_IN(PF.3) to input mode */
3838
PF->MODE &= ~(GPIO_MODE_MODE2_Msk | GPIO_MODE_MODE3_Msk);
3939
#endif
4040

41+
#if MBED_CONF_TARGET_LXT_PRESENT
4142
/* LXT Enable: Set X32_OUT(PF.4) and X32_IN(PF.5) to input mode */
4243
PF->MODE &= ~(GPIO_MODE_MODE4_Msk | GPIO_MODE_MODE5_Msk);
44+
#endif
4345

4446
/* Enable HIRC clock (Internal RC 48MHz) */
4547
CLK_EnableXtalRC(CLK_PWRCTL_HIRCEN_Msk);
46-
#if defined(NU_HXT_ENABLE) && (NU_HXT_ENABLE == 1UL)
48+
#if MBED_CONF_TARGET_HXT_PRESENT
4749
/* Enable HXT clock (external XTAL 12MHz) */
4850
CLK_EnableXtalRC(CLK_PWRCTL_HXTEN_Msk);
51+
#else
52+
/* Disable HXT clock (external XTAL 12MHz) */
53+
CLK_DisableXtalRC(CLK_PWRCTL_HXTEN_Msk);
4954
#endif
50-
/* Enable LIRC for lp_ticker */
55+
/* Enable LIRC */
5156
CLK_EnableXtalRC(CLK_PWRCTL_LIRCEN_Msk);
52-
/* Enable LXT for RTC */
57+
#if MBED_CONF_TARGET_LXT_PRESENT
58+
/* Enable LXT */
5359
CLK_EnableXtalRC(CLK_PWRCTL_LXTEN_Msk);
60+
#else
61+
/* Disable LXT */
62+
CLK_DisableXtalRC(CLK_PWRCTL_LXTEN_Msk);
63+
#endif
5464

5565
/* Wait for HIRC clock ready */
5666
CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk);
57-
#if defined(NU_HXT_ENABLE) && (NU_HXT_ENABLE == 1UL)
67+
#if MBED_CONF_TARGET_HXT_PRESENT
5868
/* Wait for HXT clock ready */
5969
CLK_WaitClockReady(CLK_STATUS_HXTSTB_Msk);
6070
#endif
6171
/* Wait for LIRC clock ready */
6272
CLK_WaitClockReady(CLK_STATUS_LIRCSTB_Msk);
73+
#if MBED_CONF_TARGET_LXT_PRESENT
6374
/* Wait for LXT clock ready */
6475
CLK_WaitClockReady(CLK_STATUS_LXTSTB_Msk);
76+
#endif
6577

66-
#if defined(NU_HXT_ENABLE) && (NU_HXT_ENABLE == 1UL)
78+
#if MBED_CONF_TARGET_HXT_PRESENT
6779
/* HXT Enable: Disable digital input path of analog pin XT1_OUT to prevent leakage */
6880
GPIO_DISABLE_DIGITAL_PATH(PF, (1ul << 2));
6981
/* HXT Enable: Disable digital input path of analog pin XT1_IN to prevent leakage */
7082
GPIO_DISABLE_DIGITAL_PATH(PF, (1ul << 3));
7183
#endif
7284

85+
#if MBED_CONF_TARGET_LXT_PRESENT
7386
/* LXT Enable: Disable digital input path of analog pin X32_OUT to prevent leakage */
7487
GPIO_DISABLE_DIGITAL_PATH(PF, (1ul << 4));
7588
/* LXT Enable: Disable digital input path of analog pin XT32_IN to prevent leakage */
7689
GPIO_DISABLE_DIGITAL_PATH(PF, (1ul << 5));
90+
#endif
7791

7892
/* Select HCLK clock source as HIRC and HCLK clock divider as 1 */
7993
CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_HIRC, CLK_CLKDIV0_HCLK(1));

‎targets/TARGET_NUVOTON/TARGET_M251/rtc_api.c

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -26,6 +26,14 @@
2626
#include "nu_miscutil.h"
2727
#include "mbed_mktime.h"
2828

29+
/* Not support LIRC-clocked RTC
30+
*
31+
* H/W doesn't support this path.
32+
*/
33+
#if !MBED_CONF_TARGET_LXT_PRESENT
34+
#error "RTC can only clock by LXT but LXT is not present. Try disabling RTC by \"device_has_remove\" in mbed_app.json"
35+
#endif
36+
2937
/* Micro seconds per second */
3038
#define NU_US_PER_SEC 1000000
3139
/* Timer clock per second

‎targets/TARGET_NUVOTON/TARGET_M261/lp_ticker.c

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -30,7 +30,11 @@
3030
/* Timer clock per lp_ticker tick */
3131
#define NU_TMRCLK_PER_TICK 1
3232
/* Timer clock per second */
33+
#if MBED_CONF_TARGET_LXT_PRESENT
3334
#define NU_TMRCLK_PER_SEC (__LXT)
35+
#else
36+
#define NU_TMRCLK_PER_SEC (__LIRC)
37+
#endif
3438
/* Timer max counter bit size */
3539
#define NU_TMR_MAXCNT_BITSIZE 24
3640
/* Timer max counter */
@@ -40,7 +44,11 @@
4044
static void tmr1_vec(void);
4145

4246
/* NOTE: To wake the system from power down mode, timer clock source must be ether LXT or LIRC. */
47+
#if MBED_CONF_TARGET_LXT_PRESENT
4348
static const struct nu_modinit_s timer1_modinit = {TIMER_1, TMR1_MODULE, CLK_CLKSEL1_TMR1SEL_LXT, 0, TMR1_RST, TMR1_IRQn, (void *) tmr1_vec};
49+
#else
50+
static const struct nu_modinit_s timer1_modinit = {TIMER_1, TMR1_MODULE, CLK_CLKSEL1_TMR1SEL_LIRC, 0, TMR1_RST, TMR1_IRQn, (void *) tmr1_vec};
51+
#endif
4452

4553
#define TIMER_MODINIT timer1_modinit
4654

‎targets/TARGET_NUVOTON/TARGET_M261/mbed_overrides.c

Lines changed: 16 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -36,23 +36,37 @@ void mbed_sdk_init(void)
3636

3737
/* Enable HIRC clock (Internal RC 12MHz) */
3838
CLK_EnableXtalRC(CLK_PWRCTL_HIRCEN_Msk);
39+
#if MBED_CONF_TARGET_HXT_PRESENT
3940
/* Enable HXT clock (external XTAL 12MHz) */
4041
CLK_EnableXtalRC(CLK_PWRCTL_HXTEN_Msk);
41-
/* Enable LIRC for lp_ticker */
42+
#else
43+
/* Disable HXT clock (external XTAL 12MHz) */
44+
CLK_DisableXtalRC(CLK_PWRCTL_HXTEN_Msk);
45+
#endif
46+
/* Enable LIRC */
4247
CLK_EnableXtalRC(CLK_PWRCTL_LIRCEN_Msk);
43-
/* Enable LXT for RTC */
48+
#if MBED_CONF_TARGET_LXT_PRESENT
49+
/* Enable LXT */
4450
CLK_EnableXtalRC(CLK_PWRCTL_LXTEN_Msk);
51+
#else
52+
/* Disable LXT */
53+
CLK_DisableXtalRC(CLK_PWRCTL_LXTEN_Msk);
54+
#endif
4555
/* Enable HIRC48 clock (Internal RC 48MHz) */
4656
CLK_EnableXtalRC(CLK_PWRCTL_HIRC48EN_Msk);
4757

4858
/* Wait for HIRC clock ready */
4959
CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk);
60+
#if MBED_CONF_TARGET_HXT_PRESENT
5061
/* Wait for HXT clock ready */
5162
CLK_WaitClockReady(CLK_STATUS_HXTSTB_Msk);
63+
#endif
5264
/* Wait for LIRC clock ready */
5365
CLK_WaitClockReady(CLK_STATUS_LIRCSTB_Msk);
66+
#if MBED_CONF_TARGET_LXT_PRESENT
5467
/* Wait for LXT clock ready */
5568
CLK_WaitClockReady(CLK_STATUS_LXTSTB_Msk);
69+
#endif
5670
/* Wait for HIRC48 clock ready */
5771
CLK_WaitClockReady(CLK_STATUS_HIRC48STB_Msk);
5872

‎targets/TARGET_NUVOTON/TARGET_M261/rtc_api.c

Lines changed: 18 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -25,13 +25,27 @@
2525
#include "nu_miscutil.h"
2626
#include "mbed_mktime.h"
2727

28+
/* Not support LIRC-clocked RTC
29+
*
30+
* Though H/W supports this path, it is still not supported because:
31+
* 1. RTC is trimmed only for 32.768 KHz LXT, not for other clock rates.
32+
* 2. RTC's clock source will reset to default LXT on reset. This results in rtc_reset test failing.
33+
*/
34+
#if !MBED_CONF_TARGET_LXT_PRESENT
35+
#error "RTC can only clock by LXT but LXT is not present. Try disabling RTC by \"device_has_remove\" in mbed_app.json"
36+
#endif
37+
2838
/* Micro seconds per second */
2939
#define NU_US_PER_SEC 1000000
3040
/* Timer clock per second
3141
*
3242
* NOTE: This dependents on real hardware.
3343
*/
44+
#if MBED_CONF_TARGET_LXT_PRESENT
3445
#define NU_RTCCLK_PER_SEC __LXT
46+
#else
47+
#define NU_RTCCLK_PER_SEC __LIRC
48+
#endif
3549

3650
/* Strategy for implementation of RTC HAL
3751
*
@@ -85,7 +99,11 @@ static time_t t_write = 0;
8599
/* Convert date time from H/W RTC to struct TM */
86100
static void rtc_convert_datetime_hwrtc_to_tm(struct tm *datetime_tm, const S_RTC_TIME_DATA_T *datetime_hwrtc);
87101

102+
#if MBED_CONF_TARGET_LXT_PRESENT
88103
static const struct nu_modinit_s rtc_modinit = {RTC_0, RTC_MODULE, CLK_CLKSEL3_RTCSEL_LXT, 0, 0, RTC_IRQn, NULL};
104+
#else
105+
static const struct nu_modinit_s rtc_modinit = {RTC_0, RTC_MODULE, CLK_CLKSEL3_RTCSEL_LIRC, 0, 0, RTC_IRQn, NULL};
106+
#endif
89107

90108
void rtc_init(void)
91109
{

‎targets/TARGET_NUVOTON/TARGET_M261/trng_api.cpp

Lines changed: 19 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -48,6 +48,25 @@ void trng_init(MBED_UNUSED trng_t *obj)
4848
/* Reset IP */
4949
SYS_ResetModule(trng_modinit.rsetidx);
5050

51+
#if MBED_CONF_TARGET_LXT_PRESENT
52+
/* 32K clock from (external) LXT */
53+
#else
54+
/* 32K clock from LIRC32 */
55+
56+
/* Unlock protected registers */
57+
SYS_UnlockReg();
58+
59+
/* To access RTC registers, clock must be enabled first. */
60+
CLK_EnableModuleClock(RTC_MODULE);
61+
62+
/* Enable 32K clock from LIRC32 */
63+
RTC->LXTCTL |= (RTC_LXTCTL_C32KS_Msk | RTC_LXTCTL_LIRC32KEN_Msk);
64+
CLK_WaitClockReady(CLK_STATUS_LIRC32STB_Msk | CLK_STATUS_LXTSTB_Msk);
65+
66+
/* Lock protected registers */
67+
SYS_LockReg();
68+
#endif
69+
5170
TRNG_T *trng_base = (TRNG_T *) NU_MODBASE(trng_modinit.modname);
5271

5372
trng_base->ACT |= TRNG_ACT_ACT_Msk;

‎targets/TARGET_NUVOTON/TARGET_M451/device/startup_M451Series.c

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -265,10 +265,12 @@ void Reset_Handler(void)
265265

266266
/* Disable Power-on Reset function */
267267
SYS_DISABLE_POR();
268-
268+
269+
#if MBED_CONF_TARGET_HXT_PRESENT
269270
/* HXT Crystal Type Select: INV */
270271
CLK->PWRCTL &= ~CLK_PWRCTL_HXTSELTYP_Msk;
271-
272+
#endif
273+
272274
/**
273275
* NOTE 1: Unlock is required for perhaps some register access in SystemInit().
274276
* NOTE 2: Because EBI (external SRAM) init is done in SystemInit(), SystemInit() must be called at the very start.

‎targets/TARGET_NUVOTON/TARGET_M451/device/system_M451Series.c

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -84,8 +84,10 @@ void SystemInit(void)
8484
{
8585
M32(GCR_BASE+0x14) |= BIT7;
8686
}
87+
#if MBED_CONF_TARGET_HXT_PRESENT
8788
/* Force to use INV type with HXT */
8889
CLK->PWRCTL &= ~CLK_PWRCTL_HXTSELTYP_Msk;
90+
#endif
8991
SYS_LockReg();
9092

9193

‎targets/TARGET_NUVOTON/TARGET_M451/device/system_M451Series.h

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -38,7 +38,11 @@ extern "C" {
3838
#define __SYS_OSC_CLK ( ___HSI) /* Main oscillator frequency */
3939

4040

41+
#if MBED_CONF_TARGET_HXT_PRESENT
4142
#define __SYSTEM_CLOCK (1*__HXT)
43+
#else
44+
#define __SYSTEM_CLOCK (1*__HIRC)
45+
#endif
4246

4347
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
4448
extern uint32_t CyclesPerUs; /*!< Cycles per micro second */

‎targets/TARGET_NUVOTON/TARGET_M451/lp_ticker.c

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -29,7 +29,11 @@
2929
/* Timer clock per lp_ticker tick */
3030
#define NU_TMRCLK_PER_TICK 1
3131
/* Timer clock per second */
32+
#if MBED_CONF_TARGET_LXT_PRESENT
3233
#define NU_TMRCLK_PER_SEC (__LXT)
34+
#else
35+
#define NU_TMRCLK_PER_SEC (__LIRC)
36+
#endif
3337
/* Timer max counter bit size */
3438
#define NU_TMR_MAXCNT_BITSIZE 24
3539
/* Timer max counter */
@@ -38,7 +42,11 @@
3842
static void tmr1_vec(void);
3943

4044
/* NOTE: To wake the system from power down mode, timer clock source must be ether LXT or LIRC. */
45+
#if MBED_CONF_TARGET_LXT_PRESENT
4146
static const struct nu_modinit_s timer1_modinit = {TIMER_1, TMR1_MODULE, CLK_CLKSEL1_TMR1SEL_LXT, 0, TMR1_RST, TMR1_IRQn, (void *) tmr1_vec};
47+
#else
48+
static const struct nu_modinit_s timer1_modinit = {TIMER_1, TMR1_MODULE, CLK_CLKSEL1_TMR1SEL_LIRC, 0, TMR1_RST, TMR1_IRQn, (void *) tmr1_vec};
49+
#endif
4250

4351
#define TIMER_MODINIT timer1_modinit
4452

‎targets/TARGET_NUVOTON/TARGET_M451/mbed_overrides.c

Lines changed: 16 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -33,21 +33,35 @@ void mbed_sdk_init(void)
3333

3434
/* Enable HIRC clock (Internal RC 22.1184MHz) */
3535
CLK_EnableXtalRC(CLK_PWRCTL_HIRCEN_Msk);
36+
#if MBED_CONF_TARGET_HXT_PRESENT
3637
/* Enable HXT clock (external XTAL 12MHz) */
3738
CLK_EnableXtalRC(CLK_PWRCTL_HXTEN_Msk);
38-
/* Enable LIRC for lp_ticker */
39+
#else
40+
/* Disable HXT clock (external XTAL 12MHz) */
41+
CLK_DisableXtalRC(CLK_PWRCTL_HXTEN_Msk);
42+
#endif
43+
/* Enable LIRC */
3944
CLK_EnableXtalRC(CLK_PWRCTL_LIRCEN_Msk);
40-
/* Enable LXT for RTC */
45+
#if MBED_CONF_TARGET_LXT_PRESENT
46+
/* Enable LXT */
4147
CLK_EnableXtalRC(CLK_PWRCTL_LXTEN_Msk);
48+
#else
49+
/* Disable LXT */
50+
CLK_DisableXtalRC(CLK_PWRCTL_LXTEN_Msk);
51+
#endif
4252

4353
/* Wait for HIRC clock ready */
4454
CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk);
55+
#if MBED_CONF_TARGET_HXT_PRESENT
4556
/* Wait for HXT clock ready */
4657
CLK_WaitClockReady(CLK_STATUS_HXTSTB_Msk);
58+
#endif
4759
/* Wait for LIRC clock ready */
4860
CLK_WaitClockReady(CLK_STATUS_LIRCSTB_Msk);
61+
#if MBED_CONF_TARGET_LXT_PRESENT
4962
/* Wait for LXT clock ready */
5063
CLK_WaitClockReady(CLK_STATUS_LXTSTB_Msk);
64+
#endif
5165

5266
/* Select HCLK clock source as HIRC and HCLK clock divider as 1 */
5367
CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_HIRC, CLK_CLKDIV0_HCLK(1));

‎targets/TARGET_NUVOTON/TARGET_M451/rtc_api.c

Lines changed: 18 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -24,13 +24,27 @@
2424
#include "nu_miscutil.h"
2525
#include "mbed_mktime.h"
2626

27+
/* Not support LIRC-clocked RTC
28+
*
29+
* Though H/W supports this path, it is still not supported because:
30+
* 1. RTC is trimmed only for 32.768 KHz LXT, not for other clock rates.
31+
* 2. RTC's clock source will reset to default LXT on reset. This results in rtc_reset test failing.
32+
*/
33+
#if !MBED_CONF_TARGET_LXT_PRESENT
34+
#error "RTC can only clock by LXT but LXT is not present. Try disabling RTC by \"device_has_remove\" in mbed_app.json"
35+
#endif
36+
2737
/* Micro seconds per second */
2838
#define NU_US_PER_SEC 1000000
2939
/* Timer clock per second
3040
*
3141
* NOTE: This dependents on real hardware.
3242
*/
43+
#if MBED_CONF_TARGET_LXT_PRESENT
3344
#define NU_RTCCLK_PER_SEC __LXT
45+
#else
46+
#define NU_RTCCLK_PER_SEC __LIRC
47+
#endif
3448

3549
/* Strategy for implementation of RTC HAL
3650
*
@@ -84,7 +98,11 @@ static time_t t_write = 0;
8498
/* Convert date time from H/W RTC to struct TM */
8599
static void rtc_convert_datetime_hwrtc_to_tm(struct tm *datetime_tm, const S_RTC_TIME_DATA_T *datetime_hwrtc);
86100

101+
#if MBED_CONF_TARGET_LXT_PRESENT
87102
static const struct nu_modinit_s rtc_modinit = {RTC_0, RTC_MODULE, CLK_CLKSEL3_RTCSEL_LXT, 0, 0, RTC_IRQn, NULL};
103+
#else
104+
static const struct nu_modinit_s rtc_modinit = {RTC_0, RTC_MODULE, CLK_CLKSEL3_RTCSEL_LIRC, 0, 0, RTC_IRQn, NULL};
105+
#endif
88106

89107
void rtc_init(void)
90108
{

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