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Merge pull request #12644 from macronix/macronix_ospi
Add OSPI driver to support the Octa mode of Macronix octaflash MX25LM51245G
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‎drivers/include/drivers/OSPI.h

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/* mbed Microcontroller Library
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* Copyright (c) 2006-2020 ARM Limited
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef MBED_OSPI_H
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#define MBED_OSPI_H
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#include "platform/platform.h"
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#if DEVICE_OSPI || defined(DOXYGEN_ONLY)
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#include "hal/ospi_api.h"
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#include "platform/PlatformMutex.h"
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#include "platform/SingletonPtr.h"
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#include "platform/NonCopyable.h"
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#define ONE_MHZ 1000000
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#define OSPI_NO_INST (-1)
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namespace mbed {
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/** \defgroup drivers-public-api-spi SPI
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* \ingroup drivers-public-api
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*/
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/**
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* \defgroup drivers_OSPI OSPI class
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* \ingroup drivers-public-api-spi
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* @{
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*/
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/** Type representing a OSPI instruction
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*/
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typedef int ospi_inst_t;
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/** A OSPI Driver, used for communicating with OSPI slave devices
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*
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* The default format is set to OCTO-SPI(1-1-1), and a clock frequency of 1MHz
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* Most OSPI devices will also require Chip Select which is indicated by ssel.
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*
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* @note Synchronization level: Thread safe
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*
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* Example:
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* @code
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* // Write 4 byte array to a OSPI slave, and read the response, note that each device will have its specific read/write/alt values defined
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*
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* #include "mbed.h"
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*
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* #define CMD_WRITE 0x02
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* #define CMD_READ 0x03
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* #define ADDRESS 0x1000
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*
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* // hardware ssel (where applicable)
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* OSPI ospi_device(OSPI_FLASH1_IO0, OSPI_FLASH1_IO1, OSPI_FLASH1_IO2, OSPI_FLASH1_IO3, OSPI_FLASH1_IO4, OSPI_FLASH1_IO5, OSPI_FLASH1_IO6,
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* OSPI_FLASH1_SCK, OSPI_FLASH1_CSN, OSPI_FLASH1_DQS); // io0, io1, io2, io3, io4, io5, io6, io7, sclk, ssel, dqs
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*
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*
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* int main() {
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* char tx_buf[] = { 0x11, 0x22, 0x33, 0x44 };
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* char rx_buf[4];
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* int buf_len = sizeof(tx_buf);
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*
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* ospi_status_t result = ospi_device.write(CMD_WRITE, 0, ADDRESS, tx_buf, &buf_len);
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* if (result != OSPI_STATUS_OK) {
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* printf("Write failed");
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* }
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* result = ospi_device.read(CMD_READ, 0, ADDRESS, rx_buf, &buf_len);
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* if (result != OSPI_STATUS_OK) {
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* printf("Read failed");
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* }
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*
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* }
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* @endcode
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*/
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class OSPI : private NonCopyable<OSPI> {
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public:
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/** Create a OSPI master connected to the specified pins
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*
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* io0-io3 is used to specify the Pins used for Quad SPI mode
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*
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* @param io0 1st IO pin used for sending/receiving data during data phase of a transaction
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* @param io1 2nd IO pin used for sending/receiving data during data phase of a transaction
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* @param io2 3rd IO pin used for sending/receiving data during data phase of a transaction
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* @param io3 4th IO pin used for sending/receiving data during data phase of a transaction
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* @param io4 5th IO pin used for sending/receiving data during data phase of a transaction
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* @param io5 6th IO pin used for sending/receiving data during data phase of a transaction
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* @param io6 7th IO pin used for sending/receiving data during data phase of a transaction
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* @param io7 8th IO pin used for sending/receiving data during data phase of a transaction
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* @param sclk OSPI Clock pin
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* @param ssel OSPI chip select pin
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* @param dqs OSPI dqs pin
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* @param mode Clock polarity and phase mode (0 - 3) of SPI
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* (Default: Mode=0 uses CPOL=0, CPHA=0, Mode=1 uses CPOL=1, CPHA=1)
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*
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*/
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OSPI(PinName io0, PinName io1, PinName io2, PinName io3, PinName io4, PinName io5, PinName io6, PinName io7,
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PinName sclk, PinName ssel = NC, PinName dqs = NC, int mode = 0);
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/** Create a OSPI master connected to the specified pins
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*
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* io0-io3 is used to specify the Pins used for Quad SPI mode
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*
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* @param pinmap reference to structure which holds static pinmap
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* @param mode Clock polarity and phase mode (0 - 3) of SPI
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* (Default: Mode=0 uses CPOL=0, CPHA=0, Mode=1 uses CPOL=1, CPHA=1)
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*
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*/
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OSPI(const ospi_pinmap_t &pinmap, int mode = 0);
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OSPI(const ospi_pinmap_t &&, int = 0) = delete; // prevent passing of temporary objects
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virtual ~OSPI()
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{
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}
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/** Configure the data transmission format
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*
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* @param inst_width Bus width used by instruction phase(Valid values are OSPI_CFG_BUS_SINGLE, OSPI_CFG_BUS_DUAL, OSPI_CFG_BUS_QUAD)
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* @param inst_size Size in bits used by instruction phase
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* @param address_width Bus width used by address phase(Valid values are OSPI_CFG_BUS_SINGLE, OSPI_CFG_BUS_DUAL, OSPI_CFG_BUS_QUAD)
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* @param address_size Size in bits used by address phase(Valid values are OSPI_CFG_ADDR_SIZE_8, OSPI_CFG_ADDR_SIZE_16, OSPI_CFG_ADDR_SIZE_24, OSPI_CFG_ADDR_SIZE_32)
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* @param alt_width Bus width used by alt phase(Valid values are OSPI_CFG_BUS_SINGLE, OSPI_CFG_BUS_DUAL, OSPI_CFG_BUS_QUAD)
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* @param alt_size Size in bits used by alt phase (must be a multiple of the number of bus lines indicated in alt_width)
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* @param data_width Bus width used by data phase(Valid values are OSPI_CFG_BUS_SINGLE, OSPI_CFG_BUS_DUAL, OSPI_CFG_BUS_QUAD)
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* @param dummy_cycles Number of dummy clock cycles to be used after alt phase
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*
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*/
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ospi_status_t configure_format(ospi_bus_width_t inst_width,
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ospi_inst_size_t inst_size,
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ospi_bus_width_t address_width,
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ospi_address_size_t address_size,
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ospi_bus_width_t alt_width,
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ospi_alt_size_t alt_size,
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ospi_bus_width_t data_width,
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int dummy_cycles);
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/** Set the ospi bus clock frequency
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*
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* @param hz SCLK frequency in hz (default = 1MHz)
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* @returns
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* Returns OSPI_STATUS_SUCCESS on successful, fails if the interface is already init-ed
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*/
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ospi_status_t set_frequency(int hz = ONE_MHZ);
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/** Read from OSPI peripheral with the preset read_instruction and alt_value
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*
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* @param address Address to be accessed in OSPI peripheral
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* @param rx_buffer Buffer for data to be read from the peripheral
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* @param rx_length Pointer to a variable containing the length of rx_buffer, and on return this variable will be updated with the actual number of bytes read
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*
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* @returns
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* Returns OSPI_STATUS_SUCCESS on successful reads and OSPI_STATUS_ERROR on failed reads.
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*/
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ospi_status_t read(int address, char *rx_buffer, size_t *rx_length);
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/** Write to OSPI peripheral using custom write instruction
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*
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* @param address Address to be accessed in OSPI peripheral
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* @param tx_buffer Buffer containing data to be sent to peripheral
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* @param tx_length Pointer to a variable containing the length of data to be transmitted, and on return this variable will be updated with the actual number of bytes written
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*
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* @returns
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* Returns OSPI_STATUS_SUCCESS on successful reads and OSPI_STATUS_ERROR on failed reads.
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*/
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ospi_status_t write(int address, const char *tx_buffer, size_t *tx_length);
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/** Read from OSPI peripheral using custom read instruction, alt values
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*
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* @param instruction Instruction value to be used in instruction phase. Use OSPI_NO_INST to skip the instruction phase
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* @param alt Alt value to be used in Alternate-byte phase. Use -1 for ignoring Alternate-byte phase
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* @param address Address to be accessed in OSPI peripheral
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* @param rx_buffer Buffer for data to be read from the peripheral
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* @param rx_length Pointer to a variable containing the length of rx_buffer, and on return this variable will be updated with the actual number of bytes read
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*
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* @returns
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* Returns OSPI_STATUS_SUCCESS on successful reads and OSPI_STATUS_ERROR on failed reads.
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*/
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ospi_status_t read(ospi_inst_t instruction, int alt, int address, char *rx_buffer, size_t *rx_length);
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/** Write to OSPI peripheral using custom write instruction, alt values
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*
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* @param instruction Instruction value to be used in instruction phase. Use OSPI_NO_INST to skip the instruction phase
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* @param alt Alt value to be used in Alternate-byte phase. Use -1 for ignoring Alternate-byte phase
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* @param address Address to be accessed in OSPI peripheral
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* @param tx_buffer Buffer containing data to be sent to peripheral
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* @param tx_length Pointer to a variable containing the length of data to be transmitted, and on return this variable will be updated with the actual number of bytes written
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*
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* @returns
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* Returns OSPI_STATUS_SUCCESS on successful reads and OSPI_STATUS_ERROR on failed reads.
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*/
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ospi_status_t write(ospi_inst_t instruction, int alt, int address, const char *tx_buffer, size_t *tx_length);
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/** Perform a transaction to write to an address(a control register) and get the status results
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*
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* @param instruction Instruction value to be used in instruction phase. Use OSPI_NO_INST to skip the instruction phase
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* @param address Some instruction might require address. Use -1 if no address
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* @param tx_buffer Buffer containing data to be sent to peripheral
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* @param tx_length Pointer to a variable containing the length of data to be transmitted, and on return this variable will be updated with the actual number of bytes written
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* @param rx_buffer Buffer for data to be read from the peripheral
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* @param rx_length Pointer to a variable containing the length of rx_buffer, and on return this variable will be updated with the actual number of bytes read
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*
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* @returns
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* Returns OSPI_STATUS_SUCCESS on successful reads and OSPI_STATUS_ERROR on failed reads.
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*/
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ospi_status_t command_transfer(ospi_inst_t instruction, int address, const char *tx_buffer, size_t tx_length, const char *rx_buffer, size_t rx_length);
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#if !defined(DOXYGEN_ONLY)
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protected:
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/** Acquire exclusive access to this SPI bus
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*/
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virtual void lock(void);
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/** Release exclusive access to this SPI bus
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*/
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virtual void unlock(void);
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ospi_t _ospi;
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bool acquire(void);
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static OSPI *_owner;
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static SingletonPtr<PlatformMutex> _mutex;
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ospi_bus_width_t _inst_width; //Bus width for Instruction phase
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ospi_inst_size_t _inst_size; //Instruction Size
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ospi_bus_width_t _address_width; //Bus width for Address phase
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ospi_address_size_t _address_size;
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ospi_bus_width_t _alt_width; //Bus width for Alt phase
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ospi_alt_size_t _alt_size;
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ospi_bus_width_t _data_width; //Bus width for Data phase
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ospi_command_t _ospi_command; //OSPI Hal command struct
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unsigned int _num_dummy_cycles; //Number of dummy cycles to be used
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int _hz; //Bus Frequency
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int _mode; //SPI mode
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bool _initialized;
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PinName _ospi_io0, _ospi_io1, _ospi_io2, _ospi_io3, _ospi_io4, _ospi_io5, _ospi_io6, _ospi_io7, _ospi_clk, _ospi_cs, _ospi_dqs; //IO lines, clock, chip select and dqs
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const ospi_pinmap_t *_static_pinmap;
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bool (OSPI::* _init_func)(void);
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private:
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/* Private acquire function without locking/unlocking
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* Implemented in order to avoid duplicate locking and boost performance
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*/
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bool _acquire(void);
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bool _initialize();
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bool _initialize_direct();
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/*
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* This function builds the ospi command struct to be send to Hal
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*/
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inline void _build_ospi_command(ospi_inst_t instruction, int address, int alt);
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#endif
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};
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/** @}*/
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} // namespace mbed
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#endif
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#endif

‎drivers/include/drivers/internal/SFDP.h

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unsigned int erase_type_size_arr[SFDP_MAX_NUM_OF_ERASE_TYPES]; ///< Erase sizes for all different erase types
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};
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/** JEDEC 4-byte Address Instruction Parameter Table info */
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struct sfdp_fbatbl_info {
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uint32_t addr; ///< Address
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size_t size; ///< Size
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int erase_type_4_byte_inst_arr[SFDP_MAX_NUM_OF_ERASE_TYPES]; ///< // Up To 4 Erase Types are supported by SFDP (each with its own command Instruction and Size)
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};
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/** SFDP JEDEC Parameter Table info */
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struct sfdp_hdr_info {
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sfdp_bptbl_info bptbl;
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sfdp_smptbl_info smptbl;
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sfdp_fbatbl_info fbatbl;
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};
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/** Parse SFDP Database

‎drivers/mbed_lib.json

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"qspi_csn": {
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"help": "QSPI chip select pin",
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"value": "QSPI_FLASH1_CSN"
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},
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"ospi_io0": {
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"help": "OSPI data I/O 0 pin",
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"value": "OSPI_FLASH1_IO0"
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},
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"ospi_io1": {
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"help": "OSPI data I/O 1 pin",
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"value": "OSPI_FLASH1_IO1"
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},
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"ospi_io2": {
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"help": "OSPI data I/O 2 pin",
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"value": "OSPI_FLASH1_IO2"
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},
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"ospi_io3": {
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"help": "OSPI data I/O 3 pin",
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"value": "OSPI_FLASH1_IO3"
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},
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"ospi_io4": {
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"help": "OSPI data I/O 4 pin",
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"value": "OSPI_FLASH1_IO4"
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},
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"ospi_io5": {
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"help": "OSPI data I/O 5 pin",
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"value": "OSPI_FLASH1_IO5"
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},
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"ospi_io6": {
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"help": "OSPI data I/O 6 pin",
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"value": "OSPI_FLASH1_IO6"
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},
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"ospi_io7": {
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"help": "OSPI data I/O 7 pin",
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"value": "OSPI_FLASH1_IO7"
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},
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"ospi_sck": {
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"help": "OSPI clock pin",
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"value": "OSPI_FLASH1_SCK"
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},
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"ospi_csn": {
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"help": "OSPI chip select pin",
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"value": "OSPI_FLASH1_CSN"
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},
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"ospi_dqs": {
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"help": "OSPI dqs pin",
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"value": "OSPI_FLASH1_DQS"
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}
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}
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}

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