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jeromecoutantjeromecoutant
committed
STM32H7 alignment within family
- license header update - STMOD+ connector pin addition - update pin comment for Ethernet connector issue (DISCO_H747I) - align files for each target
1 parent 0c740e7 commit 21ff11c

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-92
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9 files changed

+133
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‎targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H743xI/TARGET_NUCLEO_H743ZI/system_clock.c

Lines changed: 15 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -1,17 +1,16 @@
1-
/* mbed Microcontroller Library
2-
* Copyright (c) 2006-2017 ARM Limited
3-
*
4-
* Licensed under the Apache License, Version 2.0 (the "License");
5-
* you may not use this file except in compliance with the License.
6-
* You may obtain a copy of the License at
7-
*
8-
* http://www.apache.org/licenses/LICENSE-2.0
9-
*
10-
* Unless required by applicable law or agreed to in writing, software
11-
* distributed under the License is distributed on an "AS IS" BASIS,
12-
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13-
* See the License for the specific language governing permissions and
14-
* limitations under the License.
1+
/*
2+
******************************************************************************
3+
* @attention
4+
*
5+
* <h2><center>&copy; Copyright (c) 2018-2019 STMicroelectronics.
6+
* All rights reserved.</center></h2>
7+
*
8+
* This software component is licensed by ST under BSD 3-Clause license,
9+
* the "License"; You may not use this file except in compliance with the
10+
* License. You may obtain a copy of the License at:
11+
* opensource.org/licenses/BSD-3-Clause
12+
*
13+
******************************************************************************
1514
*/
1615

1716
/**
@@ -101,7 +100,7 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
101100
/* Configure the main internal regulator output voltage */
102101
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
103102

104-
while(!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {}
103+
while (!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {}
105104

106105
/* Enable HSE Oscillator and activate PLL with HSE as source */
107106
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI48;
@@ -136,7 +135,7 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
136135
RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2;
137136
RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2;
138137
RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2;
139-
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) {
138+
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
140139
return 0; // FAIL
141140
}
142141

‎targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H743xI/TARGET_NUCLEO_H743ZI2/system_clock.c

Lines changed: 15 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -1,17 +1,16 @@
1-
/* mbed Microcontroller Library
2-
* Copyright (c) 2006-2017 ARM Limited
3-
*
4-
* Licensed under the Apache License, Version 2.0 (the "License");
5-
* you may not use this file except in compliance with the License.
6-
* You may obtain a copy of the License at
7-
*
8-
* http://www.apache.org/licenses/LICENSE-2.0
9-
*
10-
* Unless required by applicable law or agreed to in writing, software
11-
* distributed under the License is distributed on an "AS IS" BASIS,
12-
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13-
* See the License for the specific language governing permissions and
14-
* limitations under the License.
1+
/*
2+
******************************************************************************
3+
* @attention
4+
*
5+
* <h2><center>&copy; Copyright (c) 2018-2019 STMicroelectronics.
6+
* All rights reserved.</center></h2>
7+
*
8+
* This software component is licensed by ST under BSD 3-Clause license,
9+
* the "License"; You may not use this file except in compliance with the
10+
* License. You may obtain a copy of the License at:
11+
* opensource.org/licenses/BSD-3-Clause
12+
*
13+
******************************************************************************
1514
*/
1615

1716
/**
@@ -101,7 +100,7 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
101100
/* Configure the main internal regulator output voltage */
102101
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
103102

104-
while(!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {}
103+
while (!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {}
105104

106105
/* Enable HSE Oscillator and activate PLL with HSE as source */
107106
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI48;
@@ -136,7 +135,7 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
136135
RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2;
137136
RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2;
138137
RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2;
139-
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) {
138+
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
140139
return 0; // FAIL
141140
}
142141

‎targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H743xI/cmsis_nvic.h

Lines changed: 14 additions & 29 deletions
Original file line numberDiff line numberDiff line change
@@ -1,32 +1,17 @@
1-
/* mbed Microcontroller Library
2-
*******************************************************************************
3-
* Copyright (c) 2016, STMicroelectronics
4-
* All rights reserved.
5-
*
6-
* Redistribution and use in source and binary forms, with or without
7-
* modification, are permitted provided that the following conditions are met:
8-
*
9-
* 1. Redistributions of source code must retain the above copyright notice,
10-
* this list of conditions and the following disclaimer.
11-
* 2. Redistributions in binary form must reproduce the above copyright notice,
12-
* this list of conditions and the following disclaimer in the documentation
13-
* and/or other materials provided with the distribution.
14-
* 3. Neither the name of STMicroelectronics nor the names of its contributors
15-
* may be used to endorse or promote products derived from this software
16-
* without specific prior written permission.
17-
*
18-
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19-
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20-
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
21-
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
22-
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23-
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
24-
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
25-
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
26-
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27-
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28-
*******************************************************************************
29-
*/
1+
/*
2+
******************************************************************************
3+
* @attention
4+
*
5+
* <h2><center>&copy; Copyright (c) 2018-2019 STMicroelectronics.
6+
* All rights reserved.</center></h2>
7+
*
8+
* This software component is licensed by ST under BSD 3-Clause license,
9+
* the "License"; You may not use this file except in compliance with the
10+
* License. You may obtain a copy of the License at:
11+
* opensource.org/licenses/BSD-3-Clause
12+
*
13+
******************************************************************************
14+
*/
3015

3116
#ifndef MBED_CMSIS_NVIC_H
3217
#define MBED_CMSIS_NVIC_H

‎targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H743xI/flash_data.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,7 @@
22
******************************************************************************
33
* @attention
44
*
5-
* <h2><center>&copy; Copyright (c) 2016-2019 STMicroelectronics.
5+
* <h2><center>&copy; Copyright (c) 2018-2019 STMicroelectronics.
66
* All rights reserved.</center></h2>
77
*
88
* This software component is licensed by ST under BSD 3-Clause license,

‎targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I/PeripheralPins.c

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -89,12 +89,12 @@ MBED_WEAK const PinMap PinMap_ADC[] = {
8989
{PC_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_INP10 // Connected to ULPI_STP
9090
{PC_0_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC2_INP10 // Connected to ULPI_STP
9191
{PC_0_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC3_INP10 // Connected to ULPI_STP
92-
{PC_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_INN10 // Connected to ETH_MDC/SAI4_D1
93-
{PC_1_ALT0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_INP11 // Connected to ETH_MDC/SAI4_D1
94-
{PC_1_ALT1, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC2_INN10 // Connected to ETH_MDC/SAI4_D1
95-
{PC_1_ALT2, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC2_INP11 // Connected to ETH_MDC/SAI4_D1
96-
{PC_1_ALT3, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC3_INN10 // Connected to ETH_MDC/SAI4_D1
97-
{PC_1_ALT4, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC3_INP11 // Connected to ETH_MDC/SAI4_D1
92+
{PC_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_INN10 // Connected to SAI4_D1 (default: SB8 off/SB21 on), ETH_MDC (SB8 on/SB21 off)
93+
{PC_1_ALT0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_INP11 // Connected to SAI4_D1 (default: SB8 off/SB21 on), ETH_MDC (SB8 on/SB21 off)
94+
{PC_1_ALT1, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC2_INN10 // Connected to SAI4_D1 (default: SB8 off/SB21 on), ETH_MDC (SB8 on/SB21 off)
95+
{PC_1_ALT2, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC2_INP11 // Connected to SAI4_D1 (default: SB8 off/SB21 on), ETH_MDC (SB8 on/SB21 off)
96+
{PC_1_ALT3, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC3_INN10 // Connected to SAI4_D1 (default: SB8 off/SB21 on), ETH_MDC (SB8 on/SB21 off)
97+
{PC_1_ALT4, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC3_INP11 // Connected to SAI4_D1 (default: SB8 off/SB21 on), ETH_MDC (SB8 on/SB21 off)
9898
// {PC_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_INN11 // Connected to PMOD\#3
9999
// {PC_2_ALT0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_INP12 // Connected to PMOD\#3
100100
// {PC_2_ALT1, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC2_INN11 // Connected to PMOD\#3
@@ -416,7 +416,7 @@ MBED_WEAK const PinMap PinMap_SPI_MOSI[] = {
416416
{PB_5_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF7_SPI3)}, // Connected to ULPI_D7
417417
{PB_5_ALT1, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SPI6)}, // Connected to ULPI_D7
418418
{PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to PMOD\#8
419-
{PC_1, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to ETH_MDC/SAI4_D1
419+
{PC_1, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to SAI4_D1 (default: SB8 off/SB21 on), ETH_MDC (SB8 on/SB21 off)
420420
{PC_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to PMOD\#2
421421
{PC_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, // Connected to SDIO1_CK
422422
{PD_6, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI3)},
@@ -463,7 +463,7 @@ MBED_WEAK const PinMap PinMap_SPI_SCLK[] = {
463463
{PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to ULPI_D6
464464
{PC_10, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, // Connected to SDIO1_D2
465465
{PD_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to PMOD\#18_DFSDM_CKOUT
466-
{PE_2, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, // Connected to ETH_nINT
466+
{PE_2, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, // Connected to SAI4_CK1 (default: R87 on/SB17 off), ETH_nINT (R87 off/SB17 on)
467467
{PE_12, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, // Connected to FMC_D9
468468
{PF_7, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, // Connected to QSPI_BK1_IO2
469469
{PG_11, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to ETH_TX_EN
@@ -536,7 +536,7 @@ MBED_WEAK const PinMap PinMap_QSPI_DATA1[] = {
536536
};
537537

538538
MBED_WEAK const PinMap PinMap_QSPI_DATA2[] = {
539-
{PE_2, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO2 // Connected to ETH_nINT
539+
{PE_2, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO2 // Connected to SAI4_CK1 (default: R87 on/SB17 off), ETH_nINT (R87 off/SB17 on)
540540
{PF_7, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO2 // Connected to QSPI_BK1_IO2
541541
{NC, NC, 0}
542542
};

‎targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I/PinNames.h

Lines changed: 44 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -401,7 +401,7 @@ typedef enum {
401401
ETH_CRS = PH_2,
402402
ETH_CRS_ALT0 = PA_0,
403403
ETH_CRS_DV = PA_7,
404-
ETH_MDC = PC_1,
404+
ETH_MDC = PC_1, /* not default HW - need SB8 on/SB21 off */
405405
ETH_MDIO = PA_2,
406406
ETH_PPS_OUT = PB_5,
407407
ETH_PPS_OUT_ALT0 = PG_8,
@@ -462,6 +462,49 @@ typedef enum {
462462
PWR_WKUP4 = PI_11,
463463
PWR_WKUP5 = PC_1,
464464

465+
/**** STMOD+ pins ****/
466+
#ifdef STMOD_UART_SOLDERBRIDGE
467+
STMOD_1 = PA_0,
468+
STMOD_2 = PD_5,
469+
STMOD_3 = PD_6,
470+
STMOD_4 = PD_4,
471+
#else /* default HW configuration */
472+
STMOD_1 = PA_11,
473+
STMOD_2 = PC_3,
474+
STMOD_3 = PC_2,
475+
STMOD_4 = PA_12,
476+
#endif /* STMOD_UART_SOLDERBRIDGE */
477+
// STMOD_5 is connected to GND
478+
// STMOD_6 is connected to +5V
479+
STMOD_7 = PD_12,
480+
STMOD_8 = PB_15,
481+
STMOD_9 = PB_14,
482+
STMOD_10 = PD_13,
483+
STMOD_11 = PC_6,
484+
STMOD_12 = PJ_13,
485+
STMOD_13 = PA_4,
486+
STMOD_14 = PF_8,
487+
// STMOD_15 is connected to +5V
488+
// STMOD_16 is connected to GND
489+
STMOD_17 = PC_7,
490+
STMOD_18 = PD_3,
491+
STMOD_19 = PB_9,
492+
STMOD_20 = PB_8,
493+
494+
/**** PMOD pins ****/
495+
PMOD_1 = STMOD_1,
496+
PMOD_2 = STMOD_2,
497+
PMOD_3 = STMOD_3,
498+
PMOD_4 = STMOD_4,
499+
// PMOD_5 is connected to GND
500+
// PMOD_6 is connected to +3V3
501+
PMOD_7 = STMOD_11,
502+
PMOD_8 = STMOD_12,
503+
// PMOD_9 is not connected
504+
// PMOD_10 is not connected
505+
// PMOD_11 is connected to GND
506+
// PMOD_12 is connected to +3V3
507+
465508
// Not connected
466509
NC = (int)0xFFFFFFFF
467510
} PinName;

‎targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I/system_clock.c

Lines changed: 23 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -20,12 +20,12 @@
2020
* | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal)
2121
* | 3- USE_PLL_HSI (internal 64 MHz clock)
2222
*--------------------------------------------------------------------
23-
* SYSCLK(MHz) | 400
24-
* AHBCLK (MHz) | 200
25-
* APB1CLK (MHz) | 100
26-
* APB2CLK (MHz) | 100
27-
* APB3CLK (MHz) | 100
28-
* APB4CLK (MHz) | 100
23+
* SYSCLK(MHz) | 480
24+
* AHBCLK (MHz) | 240
25+
* APB1CLK (MHz) | 120
26+
* APB2CLK (MHz) | 120
27+
* APB3CLK (MHz) | 120
28+
* APB4CLK (MHz) | 120
2929
* USB capable (48 MHz) | YES
3030
*--------------------------------------------------------------------
3131
**/
@@ -64,7 +64,6 @@ uint8_t SetSysClock_PLL_HSI(void);
6464

6565
void SetSysClock(void)
6666
{
67-
6867
#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC)
6968
/* 1- Try to start with HSE and external clock (MCO from STLink PCB part) */
7069
if (SetSysClock_PLL_HSE(1) == 0)
@@ -96,16 +95,21 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
9695
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
9796
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
9897

98+
/* Supply configuration update enable */
9999
HAL_PWREx_ConfigSupply(PWR_DIRECT_SMPS_SUPPLY);
100+
/* Configure the main internal regulator output voltage */
100101
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
102+
101103
while (!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {}
102104

103-
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
105+
/* Enable HSE Oscillator and activate PLL with HSE as source */
106+
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI48;
104107
if (bypass) {
105108
RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS;
106109
} else {
107110
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
108111
}
112+
RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
109113
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
110114
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
111115
RCC_OscInitStruct.PLL.PLLM = 5; // 5 MHz
@@ -131,23 +135,26 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
131135
RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2;
132136
RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2;
133137
RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2;
134-
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) {
138+
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
135139
return 0; // FAIL
136140
}
137141

138-
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_USB;
139-
PeriphClkInitStruct.Usart234578ClockSelection = RCC_USART234578CLKSOURCE_D2PCLK1;
142+
#if DEVICE_USBDEVICE
143+
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
140144
PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;
141145
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) {
142146
return 0; // FAIL
143147
}
144148

149+
HAL_PWREx_EnableUSBVoltageDetector();
150+
#endif /* DEVICE_USBDEVICE */
151+
145152
__HAL_RCC_CSI_ENABLE() ;
146-
147-
__HAL_RCC_SYSCFG_CLK_ENABLE() ;
148-
149-
HAL_EnableCompensationCell();
150-
153+
154+
__HAL_RCC_SYSCFG_CLK_ENABLE() ;
155+
156+
HAL_EnableCompensationCell();
157+
151158
return 1; // OK
152159
}
153160
#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */

‎targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/cmsis_nvic.h

Lines changed: 1 addition & 1 deletion
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******************************************************************************
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* @attention
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*
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* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
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* <h2><center>&copy; Copyright (c) 2018-2019 STMicroelectronics.
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* All rights reserved.</center></h2>
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*
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* This software component is licensed by ST under BSD 3-Clause license,

‎targets/targets.json

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],
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"config": {
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"d11_configuration": {
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"help": "Value:",
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"help": "Value: PB_5 for the default board configuration, PA_7 in case of solder bridge update (SB33 on/ SB35 off)",
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"value": "PB_5",
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"macro_name": "STM32_D11_SPI_ETHERNET_PIN"
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},
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"EXTRA_IDLE_STACK_REQUIRED"
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],
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"overrides": { "lpticker_delay_ticks": 0 },
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"supported_form_factors": ["ARDUINO"],
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"supported_form_factors": [
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"ARDUINO",
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"STMOD",
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"PMOD"
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],
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"detect_code": ["0814"],
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"device_has_add": [
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"ANALOGOUT",
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"EXTRA_IDLE_STACK_REQUIRED"
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],
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"overrides": { "lpticker_delay_ticks": 0 },
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"supported_form_factors": ["ARDUINO"],
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"supported_form_factors": [
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"ARDUINO",
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"STMOD",
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"PMOD"
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],
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"device_has_add": [
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"ANALOGOUT",
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"CAN",

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