Merge pull request #4510 from kegilbert/rearrange-odin-target-rebase

u-blox rearrange ODIN target

Author: sg-

targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/PeripheralNames.h renamed to targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/PeripheralNames.h

@@ -42,6 +42,9 @@ typedef enum {
     ADC_3 = (int)ADC3_BASE
 } ADCName;
 
+typedef enum {
+    DAC_1 = (int)DAC_BASE
+} DACName;
 
 typedef enum {
     UART_1 = (int)USART1_BASE,

targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/PeripheralPins.c renamed to targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/PeripheralPins.c

@@ -734,11 +734,13 @@ void SystemInit_ExtMemCtl(void)
   /* No pull-up, pull-down for PGx pins */ 
   GPIOG->PUPDR   = 0x00000000;
 
-/*-- FMC/FSMC Configuration --------------------------------------------------*/                                                                               
+/*-- FMC/FSMC Configuration --------------------------------------------------*/
   /* Enable the FMC/FSMC interface clock */
   RCC->AHB3ENR         |= 0x00000001;
-  
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) 
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+  /* Delay after an RCC peripheral clock enabling */
+  tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
   /* Configure and enable Bank1_SRAM2 */
   FMC_Bank1->BTCR[2]  = 0x00001011;
   FMC_Bank1->BTCR[3]  = 0x00000201;