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Merge pull request #9233 from jamesbeyond/fm_sdk
FastModel: update platform header, removed unwanted smsc9220 device
2 parents acd69ae + 55bd5d5 commit 26833c0

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-2546
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13 files changed

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‎targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M4/device/SMM_MPS2.h renamed to ‎targets/TARGET_ARM_FM/TARGET_FVP_MPS2/FVP_MPS2.h

Lines changed: 3 additions & 86 deletions
Original file line numberDiff line numberDiff line change
@@ -28,13 +28,10 @@
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
31-
*******************************************************************************
32-
* File: smm_mps2.h
33-
* Release: Version 1.1
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*******************************************************************************/
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36-
#ifndef __SMM_MPS2_H
37-
#define __SMM_MPS2_H
33+
#ifndef __FVP_MPS2_H
34+
#define __FVP_MPS2_H
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3936
#include "peripherallink.h" /* device specific header file */
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@@ -482,79 +479,6 @@ typedef struct
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#define I2S_ERROR_RXERR_Pos 1
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#define I2S_ERROR_RXERR_Msk (1UL<<I2S_ERROR_RXERR_Pos)
484481

485-
/******************************************************************************/
486-
/* SMSC9220 Register Definitions */
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/******************************************************************************/
488-
489-
typedef struct // SMSC LAN9220
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{
491-
__I uint32_t RX_DATA_PORT; // Receive FIFO Ports (offset 0x0)
492-
uint32_t RESERVED1[0x7];
493-
__O uint32_t TX_DATA_PORT; // Transmit FIFO Ports (offset 0x20)
494-
uint32_t RESERVED2[0x7];
495-
496-
__I uint32_t RX_STAT_PORT; // Receive FIFO status port (offset 0x40)
497-
__I uint32_t RX_STAT_PEEK; // Receive FIFO status peek (offset 0x44)
498-
__I uint32_t TX_STAT_PORT; // Transmit FIFO status port (offset 0x48)
499-
__I uint32_t TX_STAT_PEEK; // Transmit FIFO status peek (offset 0x4C)
500-
501-
__I uint32_t ID_REV; // Chip ID and Revision (offset 0x50)
502-
__IO uint32_t IRQ_CFG; // Main Interrupt Configuration (offset 0x54)
503-
__IO uint32_t INT_STS; // Interrupt Status (offset 0x58)
504-
__IO uint32_t INT_EN; // Interrupt Enable Register (offset 0x5C)
505-
uint32_t RESERVED3; // Reserved for future use (offset 0x60)
506-
__I uint32_t BYTE_TEST; // Read-only byte order testing register 87654321h (offset 0x64)
507-
__IO uint32_t FIFO_INT; // FIFO Level Interrupts (offset 0x68)
508-
__IO uint32_t RX_CFG; // Receive Configuration (offset 0x6C)
509-
__IO uint32_t TX_CFG; // Transmit Configuration (offset 0x70)
510-
__IO uint32_t HW_CFG; // Hardware Configuration (offset 0x74)
511-
__IO uint32_t RX_DP_CTL; // RX Datapath Control (offset 0x78)
512-
__I uint32_t RX_FIFO_INF; // Receive FIFO Information (offset 0x7C)
513-
__I uint32_t TX_FIFO_INF; // Transmit FIFO Information (offset 0x80)
514-
__IO uint32_t PMT_CTRL; // Power Management Control (offset 0x84)
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__IO uint32_t GPIO_CFG; // General Purpose IO Configuration (offset 0x88)
516-
__IO uint32_t GPT_CFG; // General Purpose Timer Configuration (offset 0x8C)
517-
__I uint32_t GPT_CNT; // General Purpose Timer Count (offset 0x90)
518-
uint32_t RESERVED4; // Reserved for future use (offset 0x94)
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__IO uint32_t ENDIAN; // WORD SWAP Register (offset 0x98)
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__I uint32_t FREE_RUN; // Free Run Counter (offset 0x9C)
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__I uint32_t RX_DROP; // RX Dropped Frames Counter (offset 0xA0)
522-
__IO uint32_t MAC_CSR_CMD; // MAC CSR Synchronizer Command (offset 0xA4)
523-
__IO uint32_t MAC_CSR_DATA; // MAC CSR Synchronizer Data (offset 0xA8)
524-
__IO uint32_t AFC_CFG; // Automatic Flow Control Configuration (offset 0xAC)
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__IO uint32_t E2P_CMD; // EEPROM Command (offset 0xB0)
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__IO uint32_t E2P_DATA; // EEPROM Data (offset 0xB4)
527-
528-
} SMSC9220_TypeDef;
529-
530-
// SMSC9220 MAC Registers Indices
531-
#define SMSC9220_MAC_CR 0x1
532-
#define SMSC9220_MAC_ADDRH 0x2
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#define SMSC9220_MAC_ADDRL 0x3
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#define SMSC9220_MAC_HASHH 0x4
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#define SMSC9220_MAC_HASHL 0x5
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#define SMSC9220_MAC_MII_ACC 0x6
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#define SMSC9220_MAC_MII_DATA 0x7
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#define SMSC9220_MAC_FLOW 0x8
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#define SMSC9220_MAC_VLAN1 0x9
540-
#define SMSC9220_MAC_VLAN2 0xA
541-
#define SMSC9220_MAC_WUFF 0xB
542-
#define SMSC9220_MAC_WUCSR 0xC
543-
544-
// SMSC9220 PHY Registers Indices
545-
#define SMSC9220_PHY_BCONTROL 0x0
546-
#define SMSC9220_PHY_BSTATUS 0x1
547-
#define SMSC9220_PHY_ID1 0x2
548-
#define SMSC9220_PHY_ID2 0x3
549-
#define SMSC9220_PHY_ANEG_ADV 0x4
550-
#define SMSC9220_PHY_ANEG_LPA 0x5
551-
#define SMSC9220_PHY_ANEG_EXP 0x6
552-
#define SMSC9220_PHY_MCONTROL 0x17
553-
#define SMSC9220_PHY_MSTATUS 0x18
554-
#define SMSC9220_PHY_CSINDICATE 0x27
555-
#define SMSC9220_PHY_INTSRC 0x29
556-
#define SMSC9220_PHY_INTMASK 0x30
557-
#define SMSC9220_PHY_CS 0x31
558482

559483
/******************************************************************************/
560484
/* Peripheral memory map */
@@ -573,20 +497,13 @@ __IO uint32_t E2P_DATA; // EEPROM Data (offset 0xB4)
573497
#define MPS2_SHIELD1_I2C_BASE (0x4002A000ul) /* Shield 1 I2C Base Address */
574498
#define MPS2_SCC_BASE (0x4002F000ul) /* SCC Base Address */
575499

576-
#ifdef CORTEX_M7
577-
#define SMSC9220_BASE (0xA0000000ul) /* Ethernet SMSC9220 Base Address */
578-
#else
579-
#define SMSC9220_BASE (0x40200000ul) /* Ethernet SMSC9220 Base Address */
580-
#endif
581-
582500
#define MPS2_VGA_TEXT_BUFFER (0x41000000ul) /* VGA Text Buffer Address */
583501
#define MPS2_VGA_BUFFER (0x41100000ul) /* VGA Buffer Base Address */
584502

585503
/******************************************************************************/
586504
/* Peripheral declaration */
587505
/******************************************************************************/
588506

589-
#define SMSC9220 ((SMSC9220_TypeDef *) SMSC9220_BASE )
590507
#define MPS2_TS_I2C ((MPS2_I2C_TypeDef *) MPS2_TSC_I2C_BASE )
591508
#define MPS2_AAIC_I2C ((MPS2_I2C_TypeDef *) MPS2_AAIC_I2C_BASE )
592509
#define MPS2_SHIELD0_I2C ((MPS2_I2C_TypeDef *) MPS2_SHIELD0_I2C_BASE )
@@ -611,4 +528,4 @@ __IO uint32_t E2P_DATA; // EEPROM Data (offset 0xB4)
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612529

613530

614-
#endif /* __SMM_MPS2_H */
531+
#endif /* __FVP_MPS2_H */

‎targets/TARGET_ARM_FM/TARGET_FVP_MPS2/SDK/fpga.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -22,7 +22,7 @@
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* Code implementation file for the fpga functions.
2323
*/
2424

25-
#include "SMM_MPS2.h" // MPS2 common header
25+
#include "FVP_MPS2.h" // MPS2 common header
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2727
// Function to delay n*ticks (25MHz = 40nS per tick)
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// Used for I2C drivers

‎targets/TARGET_ARM_FM/TARGET_FVP_MPS2/SDK/fpga.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -18,7 +18,7 @@
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* Code implementation file for the fpga functions.
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*/
2020

21-
#include "SMM_MPS2.h" // MPS2 common header
21+
#include "FVP_MPS2.h" // MPS2 common header
2222

2323
// Function to delay n*ticks (25MHz = 40nS per tick)
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// Used for I2C drivers

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