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jeromecoutantjeromecoutant
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STM32F7 : json clock source configuration
- default value is the same as before patch - system_stm32f7xx.c file is copied to family level with all other ST cube files - specific clock configuration is now in a new file: system_clock.c (target level)
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‎targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/TARGET_DISCO_F746NG/system_clock.c

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/* mbed Microcontroller Library
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* Copyright (c) 2006-2017 ARM Limited
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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/**
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* This file configures the system clock as follows:
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*--------------------------------------------------------------------
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* System clock source | 1- USE_PLL_HSE_EXTC (external 25 MHz clock)
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* | 2- USE_PLL_HSE_XTAL (external 25 MHz xtal)
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* | 3- USE_PLL_HSI (internal 16 MHz clock)
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*--------------------------------------------------------------------
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* SYSCLK(MHz) | 216
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* AHBCLK (MHz) | 216
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* APB1CLK (MHz) | 54
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* APB2CLK (MHz) | 108
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* USB capable (48 MHz) | YES
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*--------------------------------------------------------------------
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**/
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#include "stm32f7xx.h"
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#include "mbed_assert.h"
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/*!< Uncomment the following line if you need to relocate your vector Table in
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Internal SRAM. */
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/* #define VECT_TAB_SRAM */
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#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
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This value must be a multiple of 0x200. */
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// clock source is selected with CLOCK_SOURCE in json config
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#define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO)
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#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default)
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#define USE_PLL_HSI 0x2 // Use HSI internal clock
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#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
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uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
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#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
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#if ((CLOCK_SOURCE) & USE_PLL_HSI)
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uint8_t SetSysClock_PLL_HSI(void);
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#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
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/**
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* @brief Setup the microcontroller system
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* Initialize the Embedded Flash Interface, the PLL and update the
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* SystemFrequency variable.
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* @param None
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* @retval None
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*/
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void SystemInit(void)
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{
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/* FPU settings ------------------------------------------------------------*/
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#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
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SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
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#endif
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/* Reset the RCC clock configuration to the default reset state ------------*/
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/* Set HSION bit */
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RCC->CR |= (uint32_t)0x00000001;
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/* Reset CFGR register */
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RCC->CFGR = 0x00000000;
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/* Reset HSEON, CSSON and PLLON bits */
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RCC->CR &= (uint32_t)0xFEF6FFFF;
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/* Reset PLLCFGR register */
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RCC->PLLCFGR = 0x24003010;
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/* Reset HSEBYP bit */
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RCC->CR &= (uint32_t)0xFFFBFFFF;
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/* Disable all interrupts */
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RCC->CIR = 0x00000000;
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#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
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SystemInit_ExtMemCtl();
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#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
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/* Configure the Vector Table location add offset address ------------------*/
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#ifdef VECT_TAB_SRAM
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SCB->VTOR = RAMDTCM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
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#else
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SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
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#endif
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}
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/**
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* @brief Configures the System clock source, PLL Multiplier and Divider factors,
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* AHB/APBx prescalers and Flash settings
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* @note This function should be called only once the RCC clock configuration
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* is reset to the default reset state (done in SystemInit() function).
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* @param None
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* @retval None
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*/
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void SetSysClock(void)
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{
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#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC)
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/* 1- Try to start with HSE and external clock */
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if (SetSysClock_PLL_HSE(1) == 0)
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#endif
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{
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#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL)
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/* 2- If fail try to start with HSE and external xtal */
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if (SetSysClock_PLL_HSE(0) == 0)
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#endif
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{
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#if ((CLOCK_SOURCE) & USE_PLL_HSI)
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/* 3- If fail start with HSI clock */
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if (SetSysClock_PLL_HSI() == 0)
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#endif
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{
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while(1) {
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MBED_ASSERT(1);
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}
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}
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}
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}
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// Output clock on MCO2 pin(PC9) for debugging purpose
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// Can be visualized on uSD card CN3 connector pin 8
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//HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_4); // 216 MHz / 4 = 54 MHz
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}
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#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
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/******************************************************************************/
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/* PLL (clocked by HSE) used as System clock source */
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/******************************************************************************/
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uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
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{
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RCC_ClkInitTypeDef RCC_ClkInitStruct;
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RCC_OscInitTypeDef RCC_OscInitStruct;
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RCC_PeriphCLKInitTypeDef RCC_PeriphClkInitStruct;
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// Enable power clock
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__PWR_CLK_ENABLE();
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__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
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// Enable HSE oscillator and activate PLL with HSE as source
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RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
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if (bypass == 0) {
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RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External xtal on OSC_IN/OSC_OUT */
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} else {
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RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External clock on OSC_IN */
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}
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// Warning: this configuration is for a 25 MHz xtal clock only
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RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
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RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
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RCC_OscInitStruct.PLL.PLLM = 25; // VCO input clock = 1 MHz (25 MHz / 25)
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RCC_OscInitStruct.PLL.PLLN = 432; // VCO output clock = 432 MHz (1 MHz * 432)
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RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; // PLLCLK = 216 MHz (432 MHz / 2)
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RCC_OscInitStruct.PLL.PLLQ = 9; // USB clock = 48 MHz (432 MHz / 9) --> OK for USB
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if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
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return 0; // FAIL
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}
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// Activate the OverDrive to reach the 216 MHz Frequency
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if (HAL_PWREx_EnableOverDrive() != HAL_OK) {
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return 0; // FAIL
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}
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// Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
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RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
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RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 216 MHz
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RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 216 MHz
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RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; // 54 MHz
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RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; // 108 MHz
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if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7) != HAL_OK) {
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return 0; // FAIL
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}
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RCC_PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48;
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RCC_PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48SOURCE_PLL;
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if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInitStruct) != HAL_OK) {
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return 0; // FAIL
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}
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return 1; // OK
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}
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#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
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#if ((CLOCK_SOURCE) & USE_PLL_HSI)
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/******************************************************************************/
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/* PLL (clocked by HSI) used as System clock source */
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/******************************************************************************/
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uint8_t SetSysClock_PLL_HSI(void)
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{
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RCC_ClkInitTypeDef RCC_ClkInitStruct;
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RCC_OscInitTypeDef RCC_OscInitStruct;
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RCC_PeriphCLKInitTypeDef RCC_PeriphClkInitStruct;
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// Enable power clock
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__PWR_CLK_ENABLE();
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// Enable HSI oscillator and activate PLL with HSI as source
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RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
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RCC_OscInitStruct.HSIState = RCC_HSI_ON;
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RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
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RCC_OscInitStruct.HSICalibrationValue = 16;
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RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
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RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
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RCC_OscInitStruct.PLL.PLLM = 8; // VCO input clock = 2 MHz (16 MHz / 8)
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RCC_OscInitStruct.PLL.PLLN = 216; // VCO output clock = 432 MHz (2 MHz * 216)
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RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; // PLLCLK = 216 MHz (432 MHz / 2)
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RCC_OscInitStruct.PLL.PLLQ = 9;
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if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
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return 0; // FAIL
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}
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// Activate the OverDrive to reach the 216 MHz Frequency
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if (HAL_PWREx_EnableOverDrive() != HAL_OK) {
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return 0; // FAIL
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}
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// Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
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RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
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RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 216 MHz
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RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 216 MHz
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RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; // 54 MHz
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RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; // 108 MHz
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if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7) != HAL_OK) {
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return 0; // FAIL
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}
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RCC_PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48;
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RCC_PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48SOURCE_PLL;
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if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInitStruct) != HAL_OK) {
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return 0; // FAIL
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}
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return 1; // OK
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}
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#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */

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