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Merge branch 'master' of https://github.com/mbedmicro/mbed 
2 parents 4582e21 + 522752b commit 2791874

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‎libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/LPC11U6x.h

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‎libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/TOOLCHAIN_ARM_MICRO/TARGET_LPC11U68/LPC11U68.sct

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LR_IROM1 0x00000000 0x40000 { ; load region size_region (256k)
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ER_IROM1 0x00000000 0x40000 { ; load address = execution address
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*.o (RESET, +First)
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*(InRoot$$Sections)
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.ANY (+RO)
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}
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; 8_byte_aligned(16+47 vect * 4 bytes) = 0x100
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; 32kB (0x8000) - 0x100 = 0x7F00
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RW_IRAM1 (0x10000000+0x100) (0x8000-0x100) {
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.ANY (+RW +ZI)
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}
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}

‎libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/TOOLCHAIN_ARM_MICRO/TARGET_LPC11U68/startup_LPC11U6x.s

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;/**************************************************************************//**
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; * @file startup_LPC11U6x.s
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; * @brief CMSIS Cortex-M0+ Core Device Startup File for
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; * NXP LPC11U6x Device Series
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; * @version V1.00
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; * @date 22. October 2013
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; *
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; * @note
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; * Copyright (C) 2013 ARM Limited. All rights reserved.
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; *
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; * @par
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; * ARM Limited (ARM) is supplying this software for use with Cortex-M
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; * processor based microcontrollers. This file can be freely distributed
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; * within development tools that are supporting such ARM based processors.
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; *
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; * @par
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; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
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; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
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; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
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; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
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; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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; *
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; ******************************************************************************/
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; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
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; <h> Stack Configuration
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; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
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; </h>
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AREA STACK, NOINIT, READWRITE, ALIGN=3
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EXPORT __initial_sp
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__initial_sp EQU 0x10008000 ; Top of RAM from LPC1U68
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; <h> Heap Configuration
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; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
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; </h>
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Heap_Size EQU 0x00000000
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AREA HEAP, NOINIT, READWRITE, ALIGN=3
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__heap_base
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Heap_Mem SPACE Heap_Size
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__heap_limit
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PRESERVE8
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THUMB
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; Vector Table Mapped to Address 0 at Reset
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AREA RESET, DATA, READONLY
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EXPORT __Vectors
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__Vectors DCD __initial_sp ; Top of Stack
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DCD Reset_Handler ; Reset Handler
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DCD NMI_Handler ; NMI Handler
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DCD HardFault_Handler ; Hard Fault Handler
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD SVC_Handler ; SVCall Handler
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD PendSV_Handler ; PendSV Handler
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DCD SysTick_Handler ; SysTick Handler
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; External Interrupts
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DCD PIN_INT0_IRQHandler ; 16+ 0 GPIO pin interrupt 0
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DCD PIN_INT1_IRQHandler ; 16+ 1 GPIO pin interrupt 1
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DCD PIN_INT2_IRQHandler ; 16+ 2 GPIO pin interrupt 2
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DCD PIN_INT3_IRQHandler ; 16+ 3 GPIO pin interrupt 3
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DCD PIN_INT4_IRQHandler ; 16+ 4 GPIO pin interrupt 4
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DCD PIN_INT5_IRQHandler ; 16+ 5 GPIO pin interrupt 5
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DCD PIN_INT6_IRQHandler ; 16+ 6 GPIO pin interrupt 6
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DCD PIN_INT7_IRQHandler ; 16+ 7 GPIO pin interrupt 7
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DCD GINT0_IRQHandler ; 16+ 8 GPIO GROUP0 interrupt
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DCD GINT1_IRQHandler ; 16+ 9 GPIO GROUP1 interrupt
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DCD I2C1_IRQHandler ; 16+10 I2C1 interrupt
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DCD USART1_4_IRQHandler ; 16+11 Combined USART1 and USART4 interrupts
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DCD USART2_3_IRQHandler ; 16+12 Combined USART2 and USART3 interrupts
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DCD SCT0_1_IRQHandler ; 16+13 Combined SCT0 and SCT1 interrupts
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DCD SSP1_IRQHandler ; 16+14 SSP1 interrupt
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DCD I2C0_IRQHandler ; 16+15 I2C0 interrupt
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DCD CT16B0_IRQHandler ; 16+16 CT16B0 interrupt
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DCD CT16B1_IRQHandler ; 16+17 CT16B1 interrupt
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DCD CT32B0_IRQHandler ; 16+18 CT32B0 interrupt
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DCD CT32B1_IRQHandler ; 16+19 CT32B1 interrupt
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DCD SSP0_IRQHandler ; 16+20 SSP0 interrupt
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DCD USART0_IRQHandler ; 16+21 USART0 interrupt
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DCD USB_IRQHandler ; 16+22 USB interrupt
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DCD USB_FIQ_IRQHandler ; 16+23 USB_FIQ interrupt
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DCD ADC_A_IRQHandler ; 16+24 Combined ADC_A end-of-sequence A and threshold crossing interrupts
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DCD RTC_IRQHandler ; 16+25 RTC interrupt
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DCD BOD_WDT_IRQHandler ; 16+26 Combined BOD and WWDT interrupt
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DCD FLASH_IRQHandler ; 16+27 Combined flash and EEPROM controller interrupts
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DCD DMA_IRQHandler ; 16+28 DMA interrupt
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DCD ADC_B_IRQHandler ; 16+29 Combined ADC_A end-of-sequence A and threshold crossing interrupts
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DCD USBWAKEUP_IRQHandler ; 16+30 USB_WAKEUP interrupt
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DCD 0 ; 16+31 Reserved
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; <h> Code Read Protection
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; <o> Code Read Protection <0xFFFFFFFF=>CRP Disabled
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; <0x12345678=>CRP Level 1
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; <0x87654321=>CRP Level 2
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; <0x43218765=>CRP Level 3 (ARE YOU SURE?)
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; <0x4E697370=>NO ISP (ARE YOU SURE?)
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; </h>
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IF :LNOT::DEF:NO_CRP
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AREA |.ARM.__at_0x02FC|, CODE, READONLY
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DCD 0xFFFFFFFF
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ENDIF
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AREA |.text|, CODE, READONLY
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; Reset Handler
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Reset_Handler PROC
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EXPORT Reset_Handler [WEAK]
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IMPORT SystemInit
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IMPORT __main
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LDR R0, =SystemInit
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BLX R0
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LDR R0, =__main
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BX R0
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ENDP
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; Dummy Exception Handlers (infinite loops which can be modified)
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NMI_Handler PROC
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EXPORT NMI_Handler [WEAK]
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B .
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ENDP
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HardFault_Handler\
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PROC
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EXPORT HardFault_Handler [WEAK]
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B .
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ENDP
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SVC_Handler PROC
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EXPORT SVC_Handler [WEAK]
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B .
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ENDP
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PendSV_Handler PROC
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EXPORT PendSV_Handler [WEAK]
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B .
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ENDP
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SysTick_Handler PROC
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EXPORT SysTick_Handler [WEAK]
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B .
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ENDP
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Reserved_IRQHandler PROC
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EXPORT Reserved_IRQHandler [WEAK]
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B .
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ENDP
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Default_Handler PROC
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EXPORT PIN_INT0_IRQHandler [WEAK]
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EXPORT PIN_INT1_IRQHandler [WEAK]
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EXPORT PIN_INT2_IRQHandler [WEAK]
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EXPORT PIN_INT3_IRQHandler [WEAK]
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EXPORT PIN_INT4_IRQHandler [WEAK]
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EXPORT PIN_INT5_IRQHandler [WEAK]
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EXPORT PIN_INT6_IRQHandler [WEAK]
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EXPORT PIN_INT7_IRQHandler [WEAK]
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EXPORT GINT0_IRQHandler [WEAK]
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EXPORT GINT1_IRQHandler [WEAK]
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EXPORT I2C1_IRQHandler [WEAK]
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EXPORT USART1_4_IRQHandler [WEAK]
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EXPORT USART2_3_IRQHandler [WEAK]
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EXPORT SCT0_1_IRQHandler [WEAK]
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EXPORT SSP1_IRQHandler [WEAK]
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EXPORT I2C0_IRQHandler [WEAK]
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EXPORT CT16B0_IRQHandler [WEAK]
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EXPORT CT16B1_IRQHandler [WEAK]
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EXPORT CT32B0_IRQHandler [WEAK]
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EXPORT CT32B1_IRQHandler [WEAK]
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EXPORT SSP0_IRQHandler [WEAK]
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EXPORT USART0_IRQHandler [WEAK]
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EXPORT USB_IRQHandler [WEAK]
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EXPORT USB_FIQ_IRQHandler [WEAK]
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EXPORT ADC_A_IRQHandler [WEAK]
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EXPORT RTC_IRQHandler [WEAK]
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EXPORT BOD_WDT_IRQHandler [WEAK]
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EXPORT FLASH_IRQHandler [WEAK]
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EXPORT DMA_IRQHandler [WEAK]
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EXPORT ADC_B_IRQHandler [WEAK]
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EXPORT USBWAKEUP_IRQHandler [WEAK]
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PIN_INT0_IRQHandler
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PIN_INT1_IRQHandler
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PIN_INT2_IRQHandler
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PIN_INT3_IRQHandler
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PIN_INT4_IRQHandler
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PIN_INT5_IRQHandler
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PIN_INT6_IRQHandler
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PIN_INT7_IRQHandler
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GINT0_IRQHandler
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GINT1_IRQHandler
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I2C1_IRQHandler
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USART1_4_IRQHandler
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USART2_3_IRQHandler
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SCT0_1_IRQHandler
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SSP1_IRQHandler
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I2C0_IRQHandler
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CT16B0_IRQHandler
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CT16B1_IRQHandler
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CT32B0_IRQHandler
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CT32B1_IRQHandler
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SSP0_IRQHandler
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USART0_IRQHandler
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USB_IRQHandler
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USB_FIQ_IRQHandler
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ADC_A_IRQHandler
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RTC_IRQHandler
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BOD_WDT_IRQHandler
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FLASH_IRQHandler
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DMA_IRQHandler
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ADC_B_IRQHandler
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USBWAKEUP_IRQHandler
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B .
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ENDP
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ALIGN
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; User Initial Stack & Heap
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EXPORT __initial_sp
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EXPORT __heap_base
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EXPORT __heap_limit
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END

‎libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/TOOLCHAIN_ARM_MICRO/sys.cpp

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/* mbed Microcontroller Library - stackheap
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* Copyright (C) 2009-2011 ARM Limited. All rights reserved.
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*
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* Setup a fixed single stack/heap memory model,
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* between the top of the RW/ZI region and the stackpointer
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*/
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <rt_misc.h>
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#include <stdint.h>
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extern char Image$$RW_IRAM1$$ZI$$Limit[];
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extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
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uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
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uint32_t sp_limit = __current_sp();
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zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
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struct __initial_stackheap r;
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r.heap_base = zi_limit;
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r.heap_limit = sp_limit;
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return r;
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}
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#ifdef __cplusplus
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}
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#endif

‎libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/cmsis.h

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/* mbed Microcontroller Library - CMSIS
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* Copyright (C) 2009-2011 ARM Limited. All rights reserved.
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*
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* A generic CMSIS include header, pulling in LPC8xx specifics
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*/
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#ifndef MBED_CMSIS_H
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#define MBED_CMSIS_H
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#include "LPC11U6x.h"
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#include "cmsis_nvic.h"
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#endif

‎libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/cmsis_nvic.c

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/* mbed Microcontroller Library - cmsis_nvic for LPC11U24
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* Copyright (c) 2011 ARM Limited. All rights reserved.
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*
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* CMSIS-style functionality to support dynamic vectors
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*/
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#include "cmsis_nvic.h"
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#define NVIC_RAM_VECTOR_ADDRESS (0x10000000) // Vectors positioned at start of RAM
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#define NVIC_FLASH_VECTOR_ADDRESS (0x0) // Initial vector position in flash
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void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
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uint32_t *vectors = (uint32_t*)SCB->VTOR;
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uint32_t i;
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// Copy and switch to dynamic vectors if the first time called
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if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) {
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uint32_t *old_vectors = vectors;
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vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
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for (i=0; i<NVIC_NUM_VECTORS; i++) {
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vectors[i] = old_vectors[i];
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}
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SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
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}
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vectors[IRQn + 16] = vector;
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}
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uint32_t NVIC_GetVector(IRQn_Type IRQn) {
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uint32_t *vectors = (uint32_t*)SCB->VTOR;
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return vectors[IRQn + 16];
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}

‎libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/cmsis_nvic.h

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/* mbed Microcontroller Library - cmsis_nvic
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* Copyright (c) 2009-2011 ARM Limited. All rights reserved.
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*
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* CMSIS-style functionality to support dynamic vectors
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*/
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#ifndef MBED_CMSIS_NVIC_H
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#define MBED_CMSIS_NVIC_H
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#define NVIC_NUM_VECTORS (16 + 32) // CORE + MCU Peripherals
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#define NVIC_USER_IRQ_OFFSET 16
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#include "cmsis.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
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uint32_t NVIC_GetVector(IRQn_Type IRQn);
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#ifdef __cplusplus
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}
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#endif
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#endif

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