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[NUCLEO_L031K6] Correct hard tabs
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  • libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L031K6

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libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L031K6/system_stm32l0xx.c

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -442,7 +442,7 @@ uint8_t SetSysClock_PLL_HSI(void)
442442
!defined (STM32L011xx) && !defined (STM32L021xx)
443443
RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; /* For USB and RNG clock */
444444
#endif
445-
// PLLCLK = (16 MHz * 4)/2 = 32 MHz
445+
// PLLCLK = (16 MHz * 4)/2 = 32 MHz
446446
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
447447
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
448448
RCC_OscInitStruct.PLL.PLLMUL = RCC_PLLMUL_4;
@@ -489,7 +489,7 @@ uint8_t SetSysClock_MSI(void)
489489
return 0;
490490
}
491491

492-
/* Select MSI as system clock source and configure the HCLK, PCLK1 and PCLK2
492+
/* Select MSI as system clock source and configure the HCLK, PCLK1 and PCLK2
493493
clocks dividers */
494494
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
495495
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI; // 4 MHz
@@ -499,7 +499,7 @@ uint8_t SetSysClock_MSI(void)
499499
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0)!= HAL_OK)
500500
{
501501
/* Initialization Error */
502-
return 0;
502+
return 0;
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}
504504

505505
/* Enable Power Control clock */

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