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Add lpc821 cocorico target
Added by @ElektorLabs PR #1840, squashed manually.
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‎hal/targets.json

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}
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}
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},
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"ELEKTOR_COCORICO": {
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"core": "Cortex-M0+",
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"default_toolchain": "uARM",
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"extra_labels": ["NXP", "LPC81X"],
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"supported_toolchains": ["uARM", "GCC_ARM", "IAR"],
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"inherits": ["LPCTarget"],
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"is_disk_virtual": true,
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"detect_code": ["C000"],
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"progen": {
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"target": "cocorico",
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"uvision": {
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"template": ["uvision_microlib.uvproj.tmpl"]
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}
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}
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},
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"KL05Z": {
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"supported_form_factors": ["ARDUINO"],
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"core": "Cortex-M0+",

‎hal/targets/cmsis/TARGET_NXP/TARGET_LPC81X/TARGET_ELEKTOR_COCORICO/TOOLCHAIN_ARM_MICRO/LPC812.sct

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LR_IROM1 0x00000000 0x4000 { ; load region size_region (32k)
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ER_IROM1 0x00000000 0x4000 { ; load address = execution address
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*.o (RESET, +First)
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*(InRoot$$Sections)
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.ANY (+RO)
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}
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; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0
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; 8KB - 0xC0 = 0xF40
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RW_IRAM1 0x100000C0 0xF40 {
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.ANY (+RW +ZI)
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}
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}
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‎hal/targets/cmsis/TARGET_NXP/TARGET_LPC81X/TARGET_ELEKTOR_COCORICO/TOOLCHAIN_ARM_MICRO/startup_LPC8xx.S

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;/*****************************************************************************
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; * @file: startup_LPC8xx.s
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; * @purpose: CMSIS Cortex-M0+ Core Device Startup File
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; * for the NXP LPC8xx Device Series
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; * @version: V1.0
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; * @date: 16. Aug. 2012
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; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
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; *
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; * Copyright (C) 2012 ARM Limited. All rights reserved.
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; * ARM Limited (ARM) is supplying this software for use with Cortex-M0+
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; * processor based microcontrollers. This file can be freely distributed
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; * within development tools that are supporting such ARM based processors.
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; *
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; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
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; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
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; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
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; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
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; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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; *
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; *****************************************************************************/
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; <h> Stack Configuration
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; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
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; </h>
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Stack_Size EQU 0x00000200
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AREA STACK, NOINIT, READWRITE, ALIGN=3
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EXPORT __initial_sp
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Stack_Mem SPACE Stack_Size
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__initial_sp EQU 0x10001000
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; <h> Heap Configuration
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; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
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; </h>
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Heap_Size EQU 0x00000000
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AREA HEAP, NOINIT, READWRITE, ALIGN=3
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EXPORT __heap_base
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EXPORT __heap_limit
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__heap_base
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Heap_Mem SPACE Heap_Size
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__heap_limit
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PRESERVE8
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THUMB
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; Vector Table Mapped to Address 0 at Reset
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AREA RESET, DATA, READONLY
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EXPORT __Vectors
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__Vectors DCD __initial_sp ; Top of Stack
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DCD Reset_Handler ; Reset Handler
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DCD NMI_Handler ; NMI Handler
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DCD HardFault_Handler ; Hard Fault Handler
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD SVC_Handler ; SVCall Handler
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD PendSV_Handler ; PendSV Handler
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DCD SysTick_Handler ; SysTick Handler
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; External Interrupts
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DCD SPI0_IRQHandler ; SPI0 controller
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DCD SPI1_IRQHandler ; SPI1 controller
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DCD 0 ; Reserved
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DCD UART0_IRQHandler ; UART0
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DCD UART1_IRQHandler ; UART1
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DCD UART2_IRQHandler ; UART2
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD I2C_IRQHandler ; I2C controller
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DCD SCT_IRQHandler ; Smart Counter Timer
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DCD MRT_IRQHandler ; Multi-Rate Timer
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DCD CMP_IRQHandler ; Comparator
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DCD WDT_IRQHandler ; PIO1 (0:11)
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DCD BOD_IRQHandler ; Brown Out Detect
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DCD 0 ; Reserved
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DCD WKT_IRQHandler ; Wakeup timer
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD PININT0_IRQHandler ; PIO INT0
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DCD PININT1_IRQHandler ; PIO INT1
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DCD PININT2_IRQHandler ; PIO INT2
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DCD PININT3_IRQHandler ; PIO INT3
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DCD PININT4_IRQHandler ; PIO INT4
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DCD PININT5_IRQHandler ; PIO INT5
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DCD PININT6_IRQHandler ; PIO INT6
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DCD PININT7_IRQHandler ; PIO INT7
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IF :LNOT::DEF:NO_CRP
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AREA |.ARM.__at_0x02FC|, CODE, READONLY
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CRP_Key DCD 0xFFFFFFFF
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ENDIF
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AREA |.text|, CODE, READONLY
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; Reset Handler
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Reset_Handler PROC
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EXPORT Reset_Handler [WEAK]
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IMPORT SystemInit
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IMPORT __main
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LDR R0, =SystemInit
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BLX R0
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LDR R0, =__main
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BX R0
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ENDP
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; Dummy Exception Handlers (infinite loops which can be modified)
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; now, under COMMON lpc8xx_nmi.c and lpc8xx_nmi.h, a real NMI handler is created if NMI is enabled
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; for particular peripheral.
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;NMI_Handler PROC
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; EXPORT NMI_Handler [WEAK]
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; B .
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; ENDP
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HardFault_Handler\
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PROC
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EXPORT HardFault_Handler [WEAK]
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B .
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ENDP
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SVC_Handler PROC
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EXPORT SVC_Handler [WEAK]
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B .
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ENDP
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PendSV_Handler PROC
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EXPORT PendSV_Handler [WEAK]
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B .
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ENDP
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SysTick_Handler PROC
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EXPORT SysTick_Handler [WEAK]
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B .
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ENDP
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Default_Handler PROC
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EXPORT NMI_Handler [WEAK]
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EXPORT SPI0_IRQHandler [WEAK]
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EXPORT SPI1_IRQHandler [WEAK]
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EXPORT UART0_IRQHandler [WEAK]
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EXPORT UART1_IRQHandler [WEAK]
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EXPORT UART2_IRQHandler [WEAK]
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EXPORT I2C_IRQHandler [WEAK]
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EXPORT SCT_IRQHandler [WEAK]
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EXPORT MRT_IRQHandler [WEAK]
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EXPORT CMP_IRQHandler [WEAK]
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EXPORT WDT_IRQHandler [WEAK]
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EXPORT BOD_IRQHandler [WEAK]
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EXPORT WKT_IRQHandler [WEAK]
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EXPORT PININT0_IRQHandler [WEAK]
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EXPORT PININT1_IRQHandler [WEAK]
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EXPORT PININT2_IRQHandler [WEAK]
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EXPORT PININT3_IRQHandler [WEAK]
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EXPORT PININT4_IRQHandler [WEAK]
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EXPORT PININT5_IRQHandler [WEAK]
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EXPORT PININT6_IRQHandler [WEAK]
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EXPORT PININT7_IRQHandler [WEAK]
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NMI_Handler
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SPI0_IRQHandler
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SPI1_IRQHandler
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UART0_IRQHandler
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UART1_IRQHandler
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UART2_IRQHandler
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I2C_IRQHandler
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SCT_IRQHandler
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MRT_IRQHandler
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CMP_IRQHandler
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WDT_IRQHandler
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BOD_IRQHandler
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WKT_IRQHandler
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PININT0_IRQHandler
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PININT1_IRQHandler
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PININT2_IRQHandler
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PININT3_IRQHandler
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PININT4_IRQHandler
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PININT5_IRQHandler
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PININT6_IRQHandler
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PININT7_IRQHandler
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B .
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ENDP
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ALIGN
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END

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