Move BSP design.modus/GenSrc into its own component

Enables code examples/end user applications to override if necessary
Add BSP_DESIGN_MODUS component by default to all PSOC6 boards. Applications can remove this if necessary.

Author: Kyle Kearney

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg.c renamed to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c

@@ -0,0 +1,45 @@
+/*******************************************************************************
+* File Name: cycfg_clocks.c
+*
+* Description:
+* Clock configuration
+* This file was automatically generated and should not be modified.
+* 
+********************************************************************************
+* Copyright 2017-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#include "cycfg_clocks.h"
+
+
+void init_cycfg_clocks(void)
+{
+	Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_16_BIT, 0U);
+	Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_16_BIT, 0U, 51U);
+	Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_16_BIT, 0U);
+
+	Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_16_BIT, 1U);
+	Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_16_BIT, 1U, 77U);
+	Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_16_BIT, 1U);
+
+	Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 0U);
+	Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 0U, 0U);
+	Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 0U);
+
+	Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 1U);
+	Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 1U, 5U);
+	Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 1U);
+}

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg.h renamed to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h

@@ -0,0 +1,55 @@
+/*******************************************************************************
+* File Name: cycfg_clocks.h
+*
+* Description:
+* Clock configuration
+* This file was automatically generated and should not be modified.
+* 
+********************************************************************************
+* Copyright 2017-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#if !defined(CYCFG_CLOCKS_H)
+#define CYCFG_CLOCKS_H
+
+#include "cycfg_notices.h"
+#include "cy_sysclk.h"
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+#define CYBSP_DEBUG_UART_CLK_DIV_ENABLED 1U
+#define CYBSP_DEBUG_UART_CLK_DIV_HW CY_SYSCLK_DIV_16_BIT
+#define CYBSP_DEBUG_UART_CLK_DIV_NUM 0U
+#define CYBSP_BT_UART_CLK_DIV_ENABLED 1U
+#define CYBSP_BT_UART_CLK_DIV_HW CY_SYSCLK_DIV_16_BIT
+#define CYBSP_BT_UART_CLK_DIV_NUM 1U
+#define CYBSP_CSD_CLK_DIV_ENABLED 1U
+#define CYBSP_CSD_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
+#define CYBSP_CSD_CLK_DIV_NUM 0U
+#define CYBSP_CSD_COMM_CLK_DIV_ENABLED 1U
+#define CYBSP_CSD_COMM_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
+#define CYBSP_CSD_COMM_CLK_DIV_NUM 1U
+
+void init_cycfg_clocks(void);
+
+#if defined(__cplusplus)
+}
+#endif
+
+
+#endif /* CYCFG_CLOCKS_H */

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_clocks.c renamed to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c

@@ -0,0 +1,155 @@
+/*******************************************************************************
+* File Name: cycfg_peripherals.c
+*
+* Description:
+* Peripheral Hardware Block configuration
+* This file was automatically generated and should not be modified.
+* 
+********************************************************************************
+* Copyright 2017-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#include "cycfg_peripherals.h"
+
+cy_stc_csd_context_t cy_csd_0_context = 
+{
+	.lockKey = CY_CSD_NONE_KEY,
+};
+const cy_stc_scb_uart_config_t CYBSP_BT_UART_config = 
+{
+	.uartMode = CY_SCB_UART_STANDARD,
+	.enableMutliProcessorMode = false,
+	.smartCardRetryOnNack = false,
+	.irdaInvertRx = false,
+	.irdaEnableLowPowerReceiver = false,
+	.oversample = 8,
+	.enableMsbFirst = false,
+	.dataWidth = 8UL,
+	.parity = CY_SCB_UART_PARITY_NONE,
+	.stopBits = CY_SCB_UART_STOP_BITS_1,
+	.enableInputFilter = false,
+	.breakWidth = 11UL,
+	.dropOnFrameError = false,
+	.dropOnParityError = false,
+	.receiverAddress = 0x0UL,
+	.receiverAddressMask = 0x0UL,
+	.acceptAddrInFifo = false,
+	.enableCts = true,
+	.ctsPolarity = CY_SCB_UART_ACTIVE_LOW,
+	.rtsRxFifoLevel = 63,
+	.rtsPolarity = CY_SCB_UART_ACTIVE_LOW,
+	.rxFifoTriggerLevel = 1UL,
+	.rxFifoIntEnableMask = 0UL,
+	.txFifoTriggerLevel = 63UL,
+	.txFifoIntEnableMask = 0UL,
+};
+const cy_stc_scb_ezi2c_config_t CYBSP_CSD_COMM_config = 
+{
+	.numberOfAddresses = CY_SCB_EZI2C_ONE_ADDRESS,
+	.slaveAddress1 = 8U,
+	.slaveAddress2 = 0U,
+	.subAddressSize = CY_SCB_EZI2C_SUB_ADDR16_BITS,
+	.enableWakeFromSleep = false,
+};
+const cy_stc_scb_uart_config_t CYBSP_DEBUG_UART_config = 
+{
+	.uartMode = CY_SCB_UART_STANDARD,
+	.enableMutliProcessorMode = false,
+	.smartCardRetryOnNack = false,
+	.irdaInvertRx = false,
+	.irdaEnableLowPowerReceiver = false,
+	.oversample = 12,
+	.enableMsbFirst = false,
+	.dataWidth = 9UL,
+	.parity = CY_SCB_UART_PARITY_NONE,
+	.stopBits = CY_SCB_UART_STOP_BITS_1,
+	.enableInputFilter = false,
+	.breakWidth = 11UL,
+	.dropOnFrameError = false,
+	.dropOnParityError = false,
+	.receiverAddress = 0x0UL,
+	.receiverAddressMask = 0x0UL,
+	.acceptAddrInFifo = false,
+	.enableCts = true,
+	.ctsPolarity = CY_SCB_UART_ACTIVE_HIGH,
+	.rtsRxFifoLevel = 63,
+	.rtsPolarity = CY_SCB_UART_ACTIVE_LOW,
+	.rxFifoTriggerLevel = 63UL,
+	.rxFifoIntEnableMask = 0UL,
+	.txFifoTriggerLevel = 63UL,
+	.txFifoIntEnableMask = 0UL,
+};
+cy_en_sd_host_card_capacity_t CYBSP_RADIO_cardCapacity = CY_SD_HOST_SDSC;
+cy_en_sd_host_card_type_t CYBSP_RADIO_cardType = CY_SD_HOST_NOT_EMMC;
+uint32_t CYBSP_RADIO_rca = 0u;
+const cy_stc_sd_host_init_config_t CYBSP_RADIO_config = 
+{
+	.emmc = false,
+	.dmaType = CY_SD_HOST_DMA_SDMA,
+	.enableLedControl = false,
+};
+cy_stc_sd_host_sd_card_config_t CYBSP_RADIO_card_cfg = 
+{
+	.lowVoltageSignaling = false,
+	.busWidth = CY_SD_HOST_BUS_WIDTH_4_BIT,
+	.cardType = &CYBSP_RADIO_cardType,
+	.rca = &CYBSP_RADIO_rca,
+	.cardCapacity = &CYBSP_RADIO_cardCapacity,
+};
+const cy_stc_smif_config_t CYBSP_QSPI_config = 
+{
+	.mode = (uint32_t)CY_SMIF_NORMAL,
+	.deselectDelay = CYBSP_QSPI_DESELECT_DELAY,
+	.rxClockSel = (uint32_t)CY_SMIF_SEL_INV_INTERNAL_CLK,
+	.blockEvent = (uint32_t)CY_SMIF_BUS_ERROR,
+};
+const cy_stc_mcwdt_config_t CYBSP_MCWDT_config = 
+{
+	.c0Match = 32768U,
+	.c1Match = 32768U,
+	.c0Mode = CY_MCWDT_MODE_NONE,
+	.c1Mode = CY_MCWDT_MODE_NONE,
+	.c2ToggleBit = 16U,
+	.c2Mode = CY_MCWDT_MODE_NONE,
+	.c0ClearOnMatch = false,
+	.c1ClearOnMatch = false,
+	.c0c1Cascade = true,
+	.c1c2Cascade = false,
+};
+const cy_stc_rtc_config_t CYBSP_RTC_config = 
+{
+	.sec = 0U,
+	.min = 0U,
+	.hour = 12U,
+	.amPm = CY_RTC_AM,
+	.hrFormat = CY_RTC_24_HOURS,
+	.dayOfWeek = CY_RTC_SUNDAY,
+	.date = 1U,
+	.month = CY_RTC_JANUARY,
+	.year = 0U,
+};
+
+
+void init_cycfg_peripherals(void)
+{
+	Cy_SysClk_PeriphAssignDivider(PCLK_CSD_CLOCK, CY_SYSCLK_DIV_8_BIT, 0U);
+
+	Cy_SysClk_PeriphAssignDivider(PCLK_SCB2_CLOCK, CY_SYSCLK_DIV_16_BIT, 1U);
+
+	Cy_SysClk_PeriphAssignDivider(PCLK_SCB3_CLOCK, CY_SYSCLK_DIV_8_BIT, 1U);
+
+	Cy_SysClk_PeriphAssignDivider(PCLK_SCB5_CLOCK, CY_SYSCLK_DIV_16_BIT, 0U);
+}

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_clocks.h renamed to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h

@@ -0,0 +1,140 @@
+/*******************************************************************************
+* File Name: cycfg_peripherals.h
+*
+* Description:
+* Peripheral Hardware Block configuration
+* This file was automatically generated and should not be modified.
+* 
+********************************************************************************
+* Copyright 2017-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#if !defined(CYCFG_PERIPHERALS_H)
+#define CYCFG_PERIPHERALS_H
+
+#include "cycfg_notices.h"
+#include "cy_sysclk.h"
+#include "cy_csd.h"
+#include "cy_scb_uart.h"
+#include "cy_scb_ezi2c.h"
+#include "cy_sd_host.h"
+#include "cy_smif.h"
+#include "cy_mcwdt.h"
+#include "cy_rtc.h"
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+#define CYBSP_CAPSENSE_ENABLED 1U
+#define CY_CAPSENSE_CORE 4u
+#define CY_CAPSENSE_CPU_CLK 144000000u
+#define CY_CAPSENSE_PERI_CLK 72000000u
+#define CY_CAPSENSE_VDDA_MV 3300u
+#define CY_CAPSENSE_PERI_DIV_TYPE CY_SYSCLK_DIV_8_BIT
+#define CY_CAPSENSE_PERI_DIV_INDEX 0u
+#define Cmod_PORT GPIO_PRT7
+#define CintA_PORT GPIO_PRT7
+#define CintB_PORT GPIO_PRT7
+#define Button0_Rx0_PORT GPIO_PRT8
+#define Button0_Tx_PORT GPIO_PRT1
+#define Button1_Rx0_PORT GPIO_PRT8
+#define Button1_Tx_PORT GPIO_PRT1
+#define LinearSlider0_Sns0_PORT GPIO_PRT8
+#define LinearSlider0_Sns1_PORT GPIO_PRT8
+#define LinearSlider0_Sns2_PORT GPIO_PRT8
+#define LinearSlider0_Sns3_PORT GPIO_PRT8
+#define LinearSlider0_Sns4_PORT GPIO_PRT8
+#define Cmod_PIN 7u
+#define CintA_PIN 1u
+#define CintB_PIN 2u
+#define Button0_Rx0_PIN 1u
+#define Button0_Tx_PIN 0u
+#define Button1_Rx0_PIN 2u
+#define Button1_Tx_PIN 0u
+#define LinearSlider0_Sns0_PIN 3u
+#define LinearSlider0_Sns1_PIN 4u
+#define LinearSlider0_Sns2_PIN 5u
+#define LinearSlider0_Sns3_PIN 6u
+#define LinearSlider0_Sns4_PIN 7u
+#define Cmod_PORT_NUM 7u
+#define CintA_PORT_NUM 7u
+#define CintB_PORT_NUM 7u
+#define CYBSP_CAPSENSE_HW CSD0
+#define CYBSP_CAPSENSE_IRQ csd_interrupt_IRQn
+#define CYBSP_BT_UART_ENABLED 1U
+#define CYBSP_BT_UART_HW SCB2
+#define CYBSP_BT_UART_IRQ scb_2_interrupt_IRQn
+#define CYBSP_CSD_COMM_ENABLED 1U
+#define CYBSP_CSD_COMM_HW SCB3
+#define CYBSP_CSD_COMM_IRQ scb_3_interrupt_IRQn
+#define CYBSP_DEBUG_UART_ENABLED 1U
+#define CYBSP_DEBUG_UART_HW SCB5
+#define CYBSP_DEBUG_UART_IRQ scb_5_interrupt_IRQn
+#define CYBSP_RADIO_ENABLED 1U
+#define CYBSP_RADIO_HW SDHC0
+#define CYBSP_RADIO_IRQ sdhc_0_interrupt_general_IRQn
+#define CYBSP_QSPI_ENABLED 1U
+#define CYBSP_QSPI_HW SMIF0
+#define CYBSP_QSPI_IRQ smif_interrupt_IRQn
+#define CYBSP_QSPI_MEMORY_MODE_ALIGMENT_ERROR (0UL)
+#define CYBSP_QSPI_RX_DATA_FIFO_UNDERFLOW (0UL)
+#define CYBSP_QSPI_TX_COMMAND_FIFO_OVERFLOW (0UL)
+#define CYBSP_QSPI_TX_DATA_FIFO_OVERFLOW (0UL)
+#define CYBSP_QSPI_RX_FIFO_TRIGEER_LEVEL (0UL)
+#define CYBSP_QSPI_TX_FIFO_TRIGEER_LEVEL (0UL)
+#define CYBSP_QSPI_DATALINES0_1 (1UL)
+#define CYBSP_QSPI_DATALINES2_3 (1UL)
+#define CYBSP_QSPI_DATALINES4_5 (0UL)
+#define CYBSP_QSPI_DATALINES6_7 (0UL)
+#define CYBSP_QSPI_SS0 (1UL)
+#define CYBSP_QSPI_SS1 (0UL)
+#define CYBSP_QSPI_SS2 (0UL)
+#define CYBSP_QSPI_SS3 (0UL)
+#define CYBSP_QSPI_DESELECT_DELAY 7
+#define CYBSP_MCWDT_ENABLED 1U
+#define CYBSP_MCWDT_HW MCWDT_STRUCT0
+#define CYBSP_RTC_ENABLED 1U
+#define CYBSP_RTC_10_MONTH_OFFSET (28U)
+#define CYBSP_RTC_MONTH_OFFSET (24U)
+#define CYBSP_RTC_10_DAY_OFFSET (20U)
+#define CYBSP_RTC_DAY_OFFSET (16U)
+#define CYBSP_RTC_1000_YEAR_OFFSET (12U)
+#define CYBSP_RTC_100_YEAR_OFFSET (8U)
+#define CYBSP_RTC_10_YEAR_OFFSET (4U)
+#define CYBSP_RTC_YEAR_OFFSET (0U)
+
+extern cy_stc_csd_context_t cy_csd_0_context;
+extern const cy_stc_scb_uart_config_t CYBSP_BT_UART_config;
+extern const cy_stc_scb_ezi2c_config_t CYBSP_CSD_COMM_config;
+extern const cy_stc_scb_uart_config_t CYBSP_DEBUG_UART_config;
+extern cy_en_sd_host_card_capacity_t CYBSP_RADIO_cardCapacity;
+extern cy_en_sd_host_card_type_t CYBSP_RADIO_cardType;
+extern uint32_t CYBSP_RADIO_rca;
+extern const cy_stc_sd_host_init_config_t CYBSP_RADIO_config;
+extern cy_stc_sd_host_sd_card_config_t CYBSP_RADIO_card_cfg;
+extern const cy_stc_smif_config_t CYBSP_QSPI_config;
+extern const cy_stc_mcwdt_config_t CYBSP_MCWDT_config;
+extern const cy_stc_rtc_config_t CYBSP_RTC_config;
+
+void init_cycfg_peripherals(void);
+
+#if defined(__cplusplus)
+}
+#endif
+
+
+#endif /* CYCFG_PERIPHERALS_H */