Skip to content

Commit 2cd3e1e

Browse files
author
Kyle Kearney
committed
Update board hardware configuration
Include all configurator design files with each BSP
1 parent 6669f3c commit 2cd3e1e

File tree

89 files changed

+8815
-3715
lines changed

Some content is hidden

Large Commits have some content hidden by default. Use the searchbox below for content that may be hidden.

89 files changed

+8815
-3715
lines changed

‎features/FEATURE_BLE/targets/TARGET_Cypress/TARGET_CYW43XXX/HCIDriver.cpp

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -422,13 +422,13 @@ class HCIDriver : public cordio::CordioHCIDriver {
422422

423423
ble::vendor::cordio::CordioHCIDriver& ble_cordio_get_hci_driver() {
424424
static ble::vendor::cypress_ble::CyH4TransportDriver transport_driver(
425-
/* TX */ CY_BT_UART_TX, /* RX */ CY_BT_UART_RX,
426-
/* cts */ CY_BT_UART_CTS, /* rts */ CY_BT_UART_RTS, 115200,
427-
CY_BT_PIN_HOST_WAKE, CY_BT_PIN_DEVICE_WAKE
425+
/* TX */ CYBSP_BT_UART_TX, /* RX */ CYBSP_BT_UART_RX,
426+
/* cts */ CYBSP_BT_UART_CTS, /* rts */ CYBSP_BT_UART_RTS, 115200,
427+
CYBSP_BT_HOST_WAKE, CYBSP_BT_DEVICE_WAKE
428428
);
429429
static ble::vendor::cypress::HCIDriver hci_driver(
430430
transport_driver,
431-
/* bt_power */ CY_BT_PIN_POWER
431+
/* bt_power */ CYBSP_BT_POWER
432432
);
433433
return hci_driver;
434434
}

‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp

Lines changed: 24 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,24 @@
1+
/*******************************************************************************
2+
* File Name: cycfg.timestamp
3+
*
4+
* Description:
5+
* Sentinel file for determining if generated source is up to date.
6+
* This file was automatically generated and should not be modified.
7+
*
8+
********************************************************************************
9+
* Copyright 2017-2019 Cypress Semiconductor Corporation
10+
* SPDX-License-Identifier: Apache-2.0
11+
*
12+
* Licensed under the Apache License, Version 2.0 (the "License");
13+
* you may not use this file except in compliance with the License.
14+
* You may obtain a copy of the License at
15+
*
16+
* http://www.apache.org/licenses/LICENSE-2.0
17+
*
18+
* Unless required by applicable law or agreed to in writing, software
19+
* distributed under the License is distributed on an "AS IS" BASIS,
20+
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21+
* See the License for the specific language governing permissions and
22+
* limitations under the License.
23+
********************************************************************************/
24+

‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c

Lines changed: 34 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -24,22 +24,52 @@
2424

2525
#include "cycfg_clocks.h"
2626

27+
#if defined (CY_USING_HAL)
28+
const cyhal_resource_inst_t CYBSP_BT_UART_CLK_DIV_obj =
29+
{
30+
.type = CYHAL_RSC_CLOCK,
31+
.block_num = CYBSP_BT_UART_CLK_DIV_HW,
32+
.channel_num = CYBSP_BT_UART_CLK_DIV_NUM,
33+
};
34+
#endif //defined (CY_USING_HAL)
35+
#if defined (CY_USING_HAL)
36+
const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj =
37+
{
38+
.type = CYHAL_RSC_CLOCK,
39+
.block_num = CYBSP_CSD_CLK_DIV_HW,
40+
.channel_num = CYBSP_CSD_CLK_DIV_NUM,
41+
};
42+
#endif //defined (CY_USING_HAL)
43+
#if defined (CY_USING_HAL)
44+
const cyhal_resource_inst_t CYBSP_CSD_COMM_CLK_DIV_obj =
45+
{
46+
.type = CYHAL_RSC_CLOCK,
47+
.block_num = CYBSP_CSD_COMM_CLK_DIV_HW,
48+
.channel_num = CYBSP_CSD_COMM_CLK_DIV_NUM,
49+
};
50+
#endif //defined (CY_USING_HAL)
51+
2752

2853
void init_cycfg_clocks(void)
2954
{
30-
Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_16_BIT, 0U);
31-
Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_16_BIT, 0U, 51U);
32-
Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_16_BIT, 0U);
33-
3455
Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_16_BIT, 1U);
3556
Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_16_BIT, 1U, 77U);
3657
Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_16_BIT, 1U);
58+
#if defined (CY_USING_HAL)
59+
cyhal_hwmgr_reserve(&CYBSP_BT_UART_CLK_DIV_obj);
60+
#endif //defined (CY_USING_HAL)
3761

3862
Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 0U);
3963
Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 0U, 0U);
4064
Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 0U);
65+
#if defined (CY_USING_HAL)
66+
cyhal_hwmgr_reserve(&CYBSP_CSD_CLK_DIV_obj);
67+
#endif //defined (CY_USING_HAL)
4168

4269
Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 1U);
4370
Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 1U, 5U);
4471
Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 1U);
72+
#if defined (CY_USING_HAL)
73+
cyhal_hwmgr_reserve(&CYBSP_CSD_COMM_CLK_DIV_obj);
74+
#endif //defined (CY_USING_HAL)
4575
}

‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h

Lines changed: 13 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -27,14 +27,14 @@
2727

2828
#include "cycfg_notices.h"
2929
#include "cy_sysclk.h"
30+
#if defined (CY_USING_HAL)
31+
#include "cyhal_hwmgr.h"
32+
#endif //defined (CY_USING_HAL)
3033

3134
#if defined(__cplusplus)
3235
extern "C" {
3336
#endif
3437

35-
#define CYBSP_DEBUG_UART_CLK_DIV_ENABLED 1U
36-
#define CYBSP_DEBUG_UART_CLK_DIV_HW CY_SYSCLK_DIV_16_BIT
37-
#define CYBSP_DEBUG_UART_CLK_DIV_NUM 0U
3838
#define CYBSP_BT_UART_CLK_DIV_ENABLED 1U
3939
#define CYBSP_BT_UART_CLK_DIV_HW CY_SYSCLK_DIV_16_BIT
4040
#define CYBSP_BT_UART_CLK_DIV_NUM 1U
@@ -45,6 +45,16 @@ extern "C" {
4545
#define CYBSP_CSD_COMM_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
4646
#define CYBSP_CSD_COMM_CLK_DIV_NUM 1U
4747

48+
#if defined (CY_USING_HAL)
49+
extern const cyhal_resource_inst_t CYBSP_BT_UART_CLK_DIV_obj;
50+
#endif //defined (CY_USING_HAL)
51+
#if defined (CY_USING_HAL)
52+
extern const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj;
53+
#endif //defined (CY_USING_HAL)
54+
#if defined (CY_USING_HAL)
55+
extern const cyhal_resource_inst_t CYBSP_CSD_COMM_CLK_DIV_obj;
56+
#endif //defined (CY_USING_HAL)
57+
4858
void init_cycfg_clocks(void);
4959

5060
#if defined(__cplusplus)

‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c

Lines changed: 57 additions & 46 deletions
Original file line numberDiff line numberDiff line change
@@ -56,6 +56,14 @@ const cy_stc_scb_uart_config_t CYBSP_BT_UART_config =
5656
.txFifoTriggerLevel = 63UL,
5757
.txFifoIntEnableMask = 0UL,
5858
};
59+
#if defined (CY_USING_HAL)
60+
const cyhal_resource_inst_t CYBSP_BT_UART_obj =
61+
{
62+
.type = CYHAL_RSC_SCB,
63+
.block_num = 2U,
64+
.channel_num = 0U,
65+
};
66+
#endif //defined (CY_USING_HAL)
5967
const cy_stc_scb_ezi2c_config_t CYBSP_CSD_COMM_config =
6068
{
6169
.numberOfAddresses = CY_SCB_EZI2C_ONE_ADDRESS,
@@ -64,58 +72,29 @@ const cy_stc_scb_ezi2c_config_t CYBSP_CSD_COMM_config =
6472
.subAddressSize = CY_SCB_EZI2C_SUB_ADDR16_BITS,
6573
.enableWakeFromSleep = false,
6674
};
67-
const cy_stc_scb_uart_config_t CYBSP_DEBUG_UART_config =
68-
{
69-
.uartMode = CY_SCB_UART_STANDARD,
70-
.enableMutliProcessorMode = false,
71-
.smartCardRetryOnNack = false,
72-
.irdaInvertRx = false,
73-
.irdaEnableLowPowerReceiver = false,
74-
.oversample = 12,
75-
.enableMsbFirst = false,
76-
.dataWidth = 9UL,
77-
.parity = CY_SCB_UART_PARITY_NONE,
78-
.stopBits = CY_SCB_UART_STOP_BITS_1,
79-
.enableInputFilter = false,
80-
.breakWidth = 11UL,
81-
.dropOnFrameError = false,
82-
.dropOnParityError = false,
83-
.receiverAddress = 0x0UL,
84-
.receiverAddressMask = 0x0UL,
85-
.acceptAddrInFifo = false,
86-
.enableCts = true,
87-
.ctsPolarity = CY_SCB_UART_ACTIVE_HIGH,
88-
.rtsRxFifoLevel = 63,
89-
.rtsPolarity = CY_SCB_UART_ACTIVE_LOW,
90-
.rxFifoTriggerLevel = 63UL,
91-
.rxFifoIntEnableMask = 0UL,
92-
.txFifoTriggerLevel = 63UL,
93-
.txFifoIntEnableMask = 0UL,
94-
};
95-
cy_en_sd_host_card_capacity_t CYBSP_RADIO_cardCapacity = CY_SD_HOST_SDSC;
96-
cy_en_sd_host_card_type_t CYBSP_RADIO_cardType = CY_SD_HOST_NOT_EMMC;
97-
uint32_t CYBSP_RADIO_rca = 0u;
98-
const cy_stc_sd_host_init_config_t CYBSP_RADIO_config =
99-
{
100-
.emmc = false,
101-
.dmaType = CY_SD_HOST_DMA_SDMA,
102-
.enableLedControl = false,
103-
};
104-
cy_stc_sd_host_sd_card_config_t CYBSP_RADIO_card_cfg =
105-
{
106-
.lowVoltageSignaling = false,
107-
.busWidth = CY_SD_HOST_BUS_WIDTH_4_BIT,
108-
.cardType = &CYBSP_RADIO_cardType,
109-
.rca = &CYBSP_RADIO_rca,
110-
.cardCapacity = &CYBSP_RADIO_cardCapacity,
111-
};
75+
#if defined (CY_USING_HAL)
76+
const cyhal_resource_inst_t CYBSP_CSD_COMM_obj =
77+
{
78+
.type = CYHAL_RSC_SCB,
79+
.block_num = 3U,
80+
.channel_num = 0U,
81+
};
82+
#endif //defined (CY_USING_HAL)
11283
const cy_stc_smif_config_t CYBSP_QSPI_config =
11384
{
11485
.mode = (uint32_t)CY_SMIF_NORMAL,
11586
.deselectDelay = CYBSP_QSPI_DESELECT_DELAY,
11687
.rxClockSel = (uint32_t)CY_SMIF_SEL_INV_INTERNAL_CLK,
11788
.blockEvent = (uint32_t)CY_SMIF_BUS_ERROR,
11889
};
90+
#if defined (CY_USING_HAL)
91+
const cyhal_resource_inst_t CYBSP_QSPI_obj =
92+
{
93+
.type = CYHAL_RSC_SMIF,
94+
.block_num = 0U,
95+
.channel_num = 0U,
96+
};
97+
#endif //defined (CY_USING_HAL)
11998
const cy_stc_mcwdt_config_t CYBSP_MCWDT_config =
12099
{
121100
.c0Match = 32768U,
@@ -129,6 +108,14 @@ const cy_stc_mcwdt_config_t CYBSP_MCWDT_config =
129108
.c0c1Cascade = true,
130109
.c1c2Cascade = false,
131110
};
111+
#if defined (CY_USING_HAL)
112+
const cyhal_resource_inst_t CYBSP_MCWDT_obj =
113+
{
114+
.type = CYHAL_RSC_LPTIMER,
115+
.block_num = 0U,
116+
.channel_num = 0U,
117+
};
118+
#endif //defined (CY_USING_HAL)
132119
const cy_stc_rtc_config_t CYBSP_RTC_config =
133120
{
134121
.sec = 0U,
@@ -141,15 +128,39 @@ const cy_stc_rtc_config_t CYBSP_RTC_config =
141128
.month = CY_RTC_JANUARY,
142129
.year = 0U,
143130
};
131+
#if defined (CY_USING_HAL)
132+
const cyhal_resource_inst_t CYBSP_RTC_obj =
133+
{
134+
.type = CYHAL_RSC_RTC,
135+
.block_num = 0U,
136+
.channel_num = 0U,
137+
};
138+
#endif //defined (CY_USING_HAL)
144139

145140

146141
void init_cycfg_peripherals(void)
147142
{
148143
Cy_SysClk_PeriphAssignDivider(PCLK_CSD_CLOCK, CY_SYSCLK_DIV_8_BIT, 0U);
149144

150145
Cy_SysClk_PeriphAssignDivider(PCLK_SCB2_CLOCK, CY_SYSCLK_DIV_16_BIT, 1U);
146+
#if defined (CY_USING_HAL)
147+
cyhal_hwmgr_reserve(&CYBSP_BT_UART_obj);
148+
#endif //defined (CY_USING_HAL)
151149

152150
Cy_SysClk_PeriphAssignDivider(PCLK_SCB3_CLOCK, CY_SYSCLK_DIV_8_BIT, 1U);
151+
#if defined (CY_USING_HAL)
152+
cyhal_hwmgr_reserve(&CYBSP_CSD_COMM_obj);
153+
#endif //defined (CY_USING_HAL)
154+
155+
#if defined (CY_USING_HAL)
156+
cyhal_hwmgr_reserve(&CYBSP_QSPI_obj);
157+
#endif //defined (CY_USING_HAL)
158+
159+
#if defined (CY_USING_HAL)
160+
cyhal_hwmgr_reserve(&CYBSP_MCWDT_obj);
161+
#endif //defined (CY_USING_HAL)
153162

154-
Cy_SysClk_PeriphAssignDivider(PCLK_SCB5_CLOCK, CY_SYSCLK_DIV_16_BIT, 0U);
163+
#if defined (CY_USING_HAL)
164+
cyhal_hwmgr_reserve(&CYBSP_RTC_obj);
165+
#endif //defined (CY_USING_HAL)
155166
}

‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h

Lines changed: 30 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -29,17 +29,20 @@
2929
#include "cy_sysclk.h"
3030
#include "cy_csd.h"
3131
#include "cy_scb_uart.h"
32+
#if defined (CY_USING_HAL)
33+
#include "cyhal_hwmgr.h"
34+
#endif //defined (CY_USING_HAL)
3235
#include "cy_scb_ezi2c.h"
33-
#include "cy_sd_host.h"
3436
#include "cy_smif.h"
37+
#include "cycfg_qspi_memslot.h"
3538
#include "cy_mcwdt.h"
3639
#include "cy_rtc.h"
3740

3841
#if defined(__cplusplus)
3942
extern "C" {
4043
#endif
4144

42-
#define CYBSP_CAPSENSE_ENABLED 1U
45+
#define CYBSP_CSD_ENABLED 1U
4346
#define CY_CAPSENSE_CORE 4u
4447
#define CY_CAPSENSE_CPU_CLK 144000000u
4548
#define CY_CAPSENSE_PERI_CLK 72000000u
@@ -49,10 +52,10 @@ extern "C" {
4952
#define Cmod_PORT GPIO_PRT7
5053
#define CintA_PORT GPIO_PRT7
5154
#define CintB_PORT GPIO_PRT7
52-
#define Button0_Rx0_PORT GPIO_PRT8
53-
#define Button0_Tx_PORT GPIO_PRT1
54-
#define Button1_Rx0_PORT GPIO_PRT8
55-
#define Button1_Tx_PORT GPIO_PRT1
55+
#define Button0_Rx0_PORT GPIO_PRT1
56+
#define Button0_Tx_PORT GPIO_PRT8
57+
#define Button1_Rx0_PORT GPIO_PRT1
58+
#define Button1_Tx_PORT GPIO_PRT8
5659
#define LinearSlider0_Sns0_PORT GPIO_PRT8
5760
#define LinearSlider0_Sns1_PORT GPIO_PRT8
5861
#define LinearSlider0_Sns2_PORT GPIO_PRT8
@@ -61,10 +64,10 @@ extern "C" {
6164
#define Cmod_PIN 7u
6265
#define CintA_PIN 1u
6366
#define CintB_PIN 2u
64-
#define Button0_Rx0_PIN 1u
65-
#define Button0_Tx_PIN 0u
66-
#define Button1_Rx0_PIN 2u
67-
#define Button1_Tx_PIN 0u
67+
#define Button0_Rx0_PIN 0u
68+
#define Button0_Tx_PIN 1u
69+
#define Button1_Rx0_PIN 0u
70+
#define Button1_Tx_PIN 2u
6871
#define LinearSlider0_Sns0_PIN 3u
6972
#define LinearSlider0_Sns1_PIN 4u
7073
#define LinearSlider0_Sns2_PIN 5u
@@ -73,20 +76,14 @@ extern "C" {
7376
#define Cmod_PORT_NUM 7u
7477
#define CintA_PORT_NUM 7u
7578
#define CintB_PORT_NUM 7u
76-
#define CYBSP_CAPSENSE_HW CSD0
77-
#define CYBSP_CAPSENSE_IRQ csd_interrupt_IRQn
79+
#define CYBSP_CSD_HW CSD0
80+
#define CYBSP_CSD_IRQ csd_interrupt_IRQn
7881
#define CYBSP_BT_UART_ENABLED 1U
7982
#define CYBSP_BT_UART_HW SCB2
8083
#define CYBSP_BT_UART_IRQ scb_2_interrupt_IRQn
8184
#define CYBSP_CSD_COMM_ENABLED 1U
8285
#define CYBSP_CSD_COMM_HW SCB3
8386
#define CYBSP_CSD_COMM_IRQ scb_3_interrupt_IRQn
84-
#define CYBSP_DEBUG_UART_ENABLED 1U
85-
#define CYBSP_DEBUG_UART_HW SCB5
86-
#define CYBSP_DEBUG_UART_IRQ scb_5_interrupt_IRQn
87-
#define CYBSP_RADIO_ENABLED 1U
88-
#define CYBSP_RADIO_HW SDHC0
89-
#define CYBSP_RADIO_IRQ sdhc_0_interrupt_general_IRQn
9087
#define CYBSP_QSPI_ENABLED 1U
9188
#define CYBSP_QSPI_HW SMIF0
9289
#define CYBSP_QSPI_IRQ smif_interrupt_IRQn
@@ -119,16 +116,25 @@ extern "C" {
119116

120117
extern cy_stc_csd_context_t cy_csd_0_context;
121118
extern const cy_stc_scb_uart_config_t CYBSP_BT_UART_config;
119+
#if defined (CY_USING_HAL)
120+
extern const cyhal_resource_inst_t CYBSP_BT_UART_obj;
121+
#endif //defined (CY_USING_HAL)
122122
extern const cy_stc_scb_ezi2c_config_t CYBSP_CSD_COMM_config;
123-
extern const cy_stc_scb_uart_config_t CYBSP_DEBUG_UART_config;
124-
extern cy_en_sd_host_card_capacity_t CYBSP_RADIO_cardCapacity;
125-
extern cy_en_sd_host_card_type_t CYBSP_RADIO_cardType;
126-
extern uint32_t CYBSP_RADIO_rca;
127-
extern const cy_stc_sd_host_init_config_t CYBSP_RADIO_config;
128-
extern cy_stc_sd_host_sd_card_config_t CYBSP_RADIO_card_cfg;
123+
#if defined (CY_USING_HAL)
124+
extern const cyhal_resource_inst_t CYBSP_CSD_COMM_obj;
125+
#endif //defined (CY_USING_HAL)
129126
extern const cy_stc_smif_config_t CYBSP_QSPI_config;
127+
#if defined (CY_USING_HAL)
128+
extern const cyhal_resource_inst_t CYBSP_QSPI_obj;
129+
#endif //defined (CY_USING_HAL)
130130
extern const cy_stc_mcwdt_config_t CYBSP_MCWDT_config;
131+
#if defined (CY_USING_HAL)
132+
extern const cyhal_resource_inst_t CYBSP_MCWDT_obj;
133+
#endif //defined (CY_USING_HAL)
131134
extern const cy_stc_rtc_config_t CYBSP_RTC_config;
135+
#if defined (CY_USING_HAL)
136+
extern const cyhal_resource_inst_t CYBSP_RTC_obj;
137+
#endif //defined (CY_USING_HAL)
132138

133139
void init_cycfg_peripherals(void);
134140

0 commit comments

Comments
 (0)