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15 | 15 | ** Abstract:
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16 | 16 | ** Linker file for the Keil ARM C/C++ Compiler
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17 | 17 | **
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18 |
| -** Copyright (c) 2015 Freescale Semiconductor, Inc. |
| 18 | +** Copyright (c) 2016 Freescale Semiconductor, Inc. |
19 | 19 | ** All rights reserved.
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20 | 20 | **
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21 | 21 | ** Redistribution and use in source and binary forms, with or without modification,
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50 | 50 | */
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51 | 51 | #define __ram_vector_table__ 1
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52 | 52 |
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| 53 | +/* Heap 1/4 of ram and stack 1/8 */ |
| 54 | +#define __stack_size__ 0x800 |
| 55 | +#define __heap_size__ 0x1000 |
| 56 | + |
53 | 57 | #if (defined(__ram_vector_table__))
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54 | 58 | #define __ram_vector_table_size__ 0x00000200
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55 | 59 | #else
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71 | 75 | #define m_data_start (m_interrupts_ram_start + m_interrupts_ram_size)
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72 | 76 | #define m_data_size (0x00004000 - m_interrupts_ram_size)
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73 | 77 |
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| 78 | +/* Sizes */ |
| 79 | +#if (defined(__stack_size__)) |
| 80 | + #define Stack_Size __stack_size__ |
| 81 | +#else |
| 82 | + #define Stack_Size 0x0400 |
| 83 | +#endif |
| 84 | + |
| 85 | +#if (defined(__heap_size__)) |
| 86 | + #define Heap_Size __heap_size__ |
| 87 | +#else |
| 88 | + #define Heap_Size 0x0400 |
| 89 | +#endif |
74 | 90 |
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75 |
| -LR_m_text m_interrupts_start 0x10000 { ; load region size_region |
| 91 | +LR_m_text m_interrupts_start m_text_start+m_text_size-m_interrupts_start { ; load region size_region |
76 | 92 | VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address
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77 | 93 | * (RESET,+FIRST)
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78 | 94 | }
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79 | 95 | ER_m_flash_config m_flash_config_start FIXED m_flash_config_size { ; load address = execution address
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80 | 96 | * (FlashConfig)
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81 | 97 | }
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82 |
| - ER_m_text m_text_start FIXED m_text_size { ; load address = execution address |
| 98 | + ER_m_text m_text_start m_text_size { ; load address = execution address |
83 | 99 | * (InRoot$$Sections)
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84 | 100 | .ANY (+RO)
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85 | 101 | }
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| 102 | + |
| 103 | +#if (defined(__ram_vector_table__)) |
86 | 104 | VECTOR_RAM m_interrupts_ram_start EMPTY m_interrupts_ram_size {
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87 | 105 | }
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88 |
| - RW_IRAM1 m_data_start m_data_size { ; RW data |
| 106 | +#else |
| 107 | + VECTOR_RAM m_interrupts_start EMPTY 0 { |
| 108 | + } |
| 109 | +#endif |
| 110 | + RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data |
89 | 111 | .ANY (+RW +ZI)
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90 | 112 | }
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| 113 | + RW_IRAM1 +0 EMPTY Heap_Size { ; RW data |
| 114 | + } |
91 | 115 | }
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92 | 116 |
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