Add HAL API for qspi pinmap

Add the functions qspi_master_sclk_pinmap, qspi_master_ssel_pinmap and
qspi_master_data0_pinmap-qspi_master_data3_pinmap to all targets with
qspi support.

Author: c1728p9

hal/qspi_api.h

@@ -21,6 +21,7 @@
 #define MBED_QSPI_API_H
 
 #include "device.h"
+#include "pinmap.h"
 #include <stdbool.h>
 
 #if DEVICE_QSPI
@@ -182,6 +183,60 @@ qspi_status_t qspi_command_transfer(qspi_t *obj, const qspi_command_t *command,
  */
 qspi_status_t qspi_read(qspi_t *obj, const qspi_command_t *command, void *data, size_t *length);
 
+/** Get the pins that support QSPI SCLK
+ *
+ * Return a PinMap array of pins that support QSPI SCLK in
+ * master mode. The array is terminated with {NC, NC, 0}.
+ *
+ * @return PinMap array
+ */
+const PinMap *qspi_master_sclk_pinmap(void);
+
+/** Get the pins that support QSPI SSEL
+ *
+ * Return a PinMap array of pins that support QSPI SSEL in
+ * master mode. The array is terminated with {NC, NC, 0}.
+ *
+ * @return PinMap array
+ */
+const PinMap *qspi_master_ssel_pinmap(void);
+
+/** Get the pins that support QSPI DATA0
+ *
+ * Return a PinMap array of pins that support QSPI DATA0 in
+ * master mode. The array is terminated with {NC, NC, 0}.
+ *
+ * @return PinMap array
+ */
+const PinMap *qspi_master_data0_pinmap(void);
+
+/** Get the pins that support QSPI DATA1
+ *
+ * Return a PinMap array of pins that support QSPI DATA1 in
+ * master mode. The array is terminated with {NC, NC, 0}.
+ *
+ * @return PinMap array
+ */
+const PinMap *qspi_master_data1_pinmap(void);
+
+/** Get the pins that support QSPI DATA2
+ *
+ * Return a PinMap array of pins that support QSPI DATA2 in
+ * master mode. The array is terminated with {NC, NC, 0}.
+ *
+ * @return PinMap array
+ */
+const PinMap *qspi_master_data2_pinmap(void);
+
+/** Get the pins that support QSPI DATA3
+ *
+ * Return a PinMap array of pins that support QSPI DATA3 in
+ * master mode. The array is terminated with {NC, NC, 0}.
+ *
+ * @return PinMap array
+ */
+const PinMap *qspi_master_data3_pinmap(void);
+
 /**@}*/
 
 #ifdef __cplusplus

targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/api/qspi_api.c

@@ -399,5 +399,35 @@ qspi_status_t qspi_command_transfer(qspi_t *obj, const qspi_command_t *command,
     return QSPI_STATUS_OK;
 }
 
+const PinMap *qspi_master_sclk_pinmap()
+{
+    return PinMap_QSPI_SCLK;
+}
+
+const PinMap *qspi_master_ssel_pinmap()
+{
+    return PinMap_QSPI_SSEL;
+}
+
+const PinMap *qspi_master_data0_pinmap()
+{
+    return PinMap_QSPI_DATA0;
+}
+
+const PinMap *qspi_master_data1_pinmap()
+{
+    return PinMap_QSPI_DATA1;
+}
+
+const PinMap *qspi_master_data2_pinmap()
+{
+    return PinMap_QSPI_DATA2;
+}
+
+const PinMap *qspi_master_data3_pinmap()
+{
+    return PinMap_QSPI_DATA3;
+}
+
 #endif
 

targets/TARGET_NORDIC/TARGET_NRF5x/qspi_api.c

@@ -522,6 +522,36 @@ qspi_status_t sfdp_read(qspi_t *obj, const qspi_command_t *command, void *data,
     }
 }
 
+const PinMap *qspi_master_sclk_pinmap()
+{
+    return PinMap_QSPI_SCLK;
+}
+
+const PinMap *qspi_master_ssel_pinmap()
+{
+    return PinMap_QSPI_SSEL;
+}
+
+const PinMap *qspi_master_data0_pinmap()
+{
+    return PinMap_QSPI_DATA0;
+}
+
+const PinMap *qspi_master_data1_pinmap()
+{
+    return PinMap_QSPI_DATA1;
+}
+
+const PinMap *qspi_master_data2_pinmap()
+{
+    return PinMap_QSPI_DATA2;
+}
+
+const PinMap *qspi_master_data3_pinmap()
+{
+    return PinMap_QSPI_DATA3;
+}
+
 
 #endif
 

targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC/qspi_api.c

@@ -338,5 +338,35 @@ qspi_status_t qspi_command_transfer(qspi_t *obj, const qspi_command_t *command,
     return QSPI_STATUS_OK;
 }
 
+const PinMap *qspi_master_sclk_pinmap()
+{
+    return PinMap_QSPI_SCLK;
+}
+
+const PinMap *qspi_master_ssel_pinmap()
+{
+    return PinMap_QSPI_SSEL;
+}
+
+const PinMap *qspi_master_data0_pinmap()
+{
+    return PinMap_QSPI_DATA0;
+}
+
+const PinMap *qspi_master_data1_pinmap()
+{
+    return PinMap_QSPI_DATA1;
+}
+
+const PinMap *qspi_master_data2_pinmap()
+{
+    return PinMap_QSPI_DATA2;
+}
+
+const PinMap *qspi_master_data3_pinmap()
+{
+    return PinMap_QSPI_DATA3;
+}
+
 #endif
 

targets/TARGET_STM/qspi_api.c

@@ -320,6 +320,36 @@ qspi_status_t qspi_command_transfer(qspi_t *obj, const qspi_command_t *command,
     return status;
 }
 
+const PinMap *qspi_master_sclk_pinmap()
+{
+    return PinMap_QSPI_SCLK;
+}
+
+const PinMap *qspi_master_ssel_pinmap()
+{
+    return PinMap_QSPI_SSEL;
+}
+
+const PinMap *qspi_master_data0_pinmap()
+{
+    return PinMap_QSPI_DATA0;
+}
+
+const PinMap *qspi_master_data1_pinmap()
+{
+    return PinMap_QSPI_DATA1;
+}
+
+const PinMap *qspi_master_data2_pinmap()
+{
+    return PinMap_QSPI_DATA2;
+}
+
+const PinMap *qspi_master_data3_pinmap()
+{
+    return PinMap_QSPI_DATA3;
+}
+
 #endif
 
 /** @}*/

targets/TARGET_Silicon_Labs/TARGET_EFM32/qspi_api.c

@@ -363,4 +363,34 @@ qspi_status_t qspi_read(qspi_t *obj, const qspi_command_t *command, void *data,
     return QSPI_STATUS_OK;
 }
 
+const PinMap *qspi_master_sclk_pinmap()
+{
+    return PinMap_QSPI_SCLK;
+}
+
+const PinMap *qspi_master_ssel_pinmap()
+{
+    return PinMap_QSPI_CS0;
+}
+
+const PinMap *qspi_master_data0_pinmap()
+{
+    return PinMap_QSPI_DQ0;
+}
+
+const PinMap *qspi_master_data1_pinmap()
+{
+    return PinMap_QSPI_DQ1;
+}
+
+const PinMap *qspi_master_data2_pinmap()
+{
+    return PinMap_QSPI_DQ2;
+}
+
+const PinMap *qspi_master_data3_pinmap()
+{
+    return PinMap_QSPI_DQ3;
+}
+
 #endif /* DEVICE_QSPI && QSPI_PRESENT */