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JonatanAntoniTomoYamanaka
JonatanAntoni
authored and
TomoYamanaka
committed
Core(A): Refactored L1 Cache maintenance to be compiler agnostic.
- Added L1 Cache test cases to CoreValidation. - Adopted FVP Cortex-A configs to simulate cache states.
1 parent 0ff62f6 commit 2f06202

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7 files changed

+295
-385
lines changed

7 files changed

+295
-385
lines changed

‎cmsis/TARGET_CORTEX_A/cmsis_armcc.h

Lines changed: 21 additions & 77 deletions
Original file line numberDiff line numberDiff line change
@@ -37,26 +37,29 @@
3737
/* CMSIS compiler specific defines */
3838
#ifndef __ASM
3939
#define __ASM __asm
40-
#endif
41-
#ifndef __INLINE
40+
#endif
41+
#ifndef __INLINE
4242
#define __INLINE __inline
43-
#endif
44-
#ifndef __FORCEINLINE
43+
#endif
44+
#ifndef __FORCEINLINE
4545
#define __FORCEINLINE __forceinline
46-
#endif
47-
#ifndef __STATIC_INLINE
46+
#endif
47+
#ifndef __STATIC_INLINE
4848
#define __STATIC_INLINE static __inline
49-
#endif
50-
#ifndef __STATIC_FORCEINLINE
49+
#endif
50+
#ifndef __STATIC_FORCEINLINE
5151
#define __STATIC_FORCEINLINE static __forceinline
52-
#endif
53-
#ifndef __NO_RETURN
52+
#endif
53+
#ifndef __NO_RETURN
5454
#define __NO_RETURN __declspec(noreturn)
55-
#endif
56-
#ifndef __USED
55+
#endif
56+
#ifndef __DEPRECATED
57+
#define __DEPRECATED __attribute__((deprecated))
58+
#endif
59+
#ifndef __USED
5760
#define __USED __attribute__((used))
58-
#endif
59-
#ifndef __WEAK
61+
#endif
62+
#ifndef __WEAK
6063
#define __WEAK __attribute__((weak))
6164
#endif
6265
#ifndef __PACKED
@@ -79,8 +82,8 @@
7982
#endif
8083
#ifndef __ALIGNED
8184
#define __ALIGNED(x) __attribute__((aligned(x)))
82-
#endif
83-
#ifndef __PACKED
85+
#endif
86+
#ifndef __PACKED
8487
#define __PACKED __attribute__((packed))
8588
#endif
8689

@@ -378,7 +381,7 @@ __STATIC_INLINE __ASM uint32_t __get_SP(void)
378381
BX lr
379382
}
380383

381-
/** \brief Set Stack Pointer
384+
/** \brief Set Stack Pointer
382385
\param [in] stack Stack Pointer value to set
383386
*/
384387
__STATIC_INLINE __ASM void __set_SP(uint32_t stack)
@@ -447,7 +450,7 @@ __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
447450
/*
448451
* Include common core functions to access Coprocessor 15 registers
449452
*/
450-
453+
451454
#define __get_CP(cp, op1, Rt, CRn, CRm, op2) do { register uint32_t tmp __ASM("cp" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2); (Rt) = tmp; } while(0)
452455
#define __set_CP(cp, op1, Rt, CRn, CRm, op2) do { register uint32_t tmp __ASM("cp" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2); tmp = (Rt); } while(0)
453456
#define __get_CP64(cp, op1, Rt, CRm) \
@@ -467,65 +470,6 @@ __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
467470

468471
#include "cmsis_cp15.h"
469472

470-
/** \brief Clean and Invalidate the entire data or unified cache
471-
* \param [in] op 0 - invalidate, 1 - clean, otherwise - invalidate and clean
472-
*/
473-
__STATIC_INLINE __ASM void __L1C_CleanInvalidateCache(uint32_t op)
474-
{
475-
ARM
476-
477-
PUSH {R4-R11}
478-
479-
MRC p15, 1, R6, c0, c0, 1 // Read CLIDR
480-
ANDS R3, R6, #0x07000000 // Extract coherency level
481-
MOV R3, R3, LSR #23 // Total cache levels << 1
482-
BEQ Finished // If 0, no need to clean
483-
484-
MOV R10, #0 // R10 holds current cache level << 1
485-
Loop1 ADD R2, R10, R10, LSR #1 // R2 holds cache "Set" position
486-
MOV R1, R6, LSR R2 // Bottom 3 bits are the Cache-type for this level
487-
AND R1, R1, #7 // Isolate those lower 3 bits
488-
CMP R1, #2
489-
BLT Skip // No cache or only instruction cache at this level
490-
491-
MCR p15, 2, R10, c0, c0, 0 // Write the Cache Size selection register
492-
ISB // ISB to sync the change to the CacheSizeID reg
493-
MRC p15, 1, R1, c0, c0, 0 // Reads current Cache Size ID register
494-
AND R2, R1, #7 // Extract the line length field
495-
ADD R2, R2, #4 // Add 4 for the line length offset (log2 16 bytes)
496-
LDR R4, =0x3FF
497-
ANDS R4, R4, R1, LSR #3 // R4 is the max number on the way size (right aligned)
498-
CLZ R5, R4 // R5 is the bit position of the way size increment
499-
LDR R7, =0x7FFF
500-
ANDS R7, R7, R1, LSR #13 // R7 is the max number of the index size (right aligned)
501-
502-
Loop2 MOV R9, R4 // R9 working copy of the max way size (right aligned)
503-
504-
Loop3 ORR R11, R10, R9, LSL R5 // Factor in the Way number and cache number into R11
505-
ORR R11, R11, R7, LSL R2 // Factor in the Set number
506-
CMP R0, #0
507-
BNE Dccsw
508-
MCR p15, 0, R11, c7, c6, 2 // DCISW. Invalidate by Set/Way
509-
B cont
510-
Dccsw CMP R0, #1
511-
BNE Dccisw
512-
MCR p15, 0, R11, c7, c10, 2 // DCCSW. Clean by Set/Way
513-
B cont
514-
Dccisw MCR p15, 0, R11, c7, c14, 2 // DCCISW. Clean and Invalidate by Set/Way
515-
cont SUBS R9, R9, #1 // Decrement the Way number
516-
BGE Loop3
517-
SUBS R7, R7, #1 // Decrement the Set number
518-
BGE Loop2
519-
Skip ADD R10, R10, #2 // Increment the cache number
520-
CMP R3, R10
521-
BGT Loop1
522-
523-
Finished
524-
DSB
525-
POP {R4-R11}
526-
BX lr
527-
}
528-
529473
/** \brief Enable Floating Point Unit
530474
531475
Critical section, called from undef handler, so systick is disabled

‎cmsis/TARGET_CORTEX_A/cmsis_armclang.h

Lines changed: 20 additions & 77 deletions
Original file line numberDiff line numberDiff line change
@@ -34,26 +34,29 @@
3434
/* CMSIS compiler specific defines */
3535
#ifndef __ASM
3636
#define __ASM __asm
37-
#endif
38-
#ifndef __INLINE
37+
#endif
38+
#ifndef __INLINE
3939
#define __INLINE __inline
40-
#endif
41-
#ifndef __FORCEINLINE
40+
#endif
41+
#ifndef __FORCEINLINE
4242
#define __FORCEINLINE __attribute__((always_inline))
43-
#endif
44-
#ifndef __STATIC_INLINE
43+
#endif
44+
#ifndef __STATIC_INLINE
4545
#define __STATIC_INLINE static __inline
46-
#endif
47-
#ifndef __STATIC_FORCEINLINE
46+
#endif
47+
#ifndef __STATIC_FORCEINLINE
4848
#define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline
49-
#endif
50-
#ifndef __NO_RETURN
51-
#define __NO_RETURN __declspec(noreturn)
52-
#endif
53-
#ifndef __USED
49+
#endif
50+
#ifndef __NO_RETURN
51+
#define __NO_RETURN __attribute__((__noreturn__))
52+
#endif
53+
#ifndef __DEPRECATED
54+
#define __DEPRECATED __attribute__((deprecated))
55+
#endif
56+
#ifndef __USED
5457
#define __USED __attribute__((used))
55-
#endif
56-
#ifndef __WEAK
58+
#endif
59+
#ifndef __WEAK
5760
#define __WEAK __attribute__((weak))
5861
#endif
5962
#ifndef __PACKED
@@ -95,8 +98,8 @@
9598
#endif
9699
#ifndef __ALIGNED
97100
#define __ALIGNED(x) __attribute__((aligned(x)))
98-
#endif
99-
#ifndef __PACKED
101+
#endif
102+
#ifndef __PACKED
100103
#define __PACKED __attribute__((packed))
101104
#endif
102105

@@ -428,66 +431,6 @@ __STATIC_FORCEINLINE void __set_FPEXC(uint32_t fpexc)
428431

429432
#include "cmsis_cp15.h"
430433

431-
432-
/** \brief Clean and Invalidate the entire data or unified cache
433-
434-
Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency
435-
*/
436-
__STATIC_INLINE void __L1C_CleanInvalidateCache(uint32_t op)
437-
{
438-
__ASM volatile(
439-
" PUSH {R4-R11} \n"
440-
441-
" MRC p15, 1, R6, c0, c0, 1 \n" // Read CLIDR
442-
" ANDS R3, R6, #0x07000000 \n" // Extract coherency level
443-
" MOV R3, R3, LSR #23 \n" // Total cache levels << 1
444-
" BEQ Finished \n" // If 0, no need to clean
445-
446-
" MOV R10, #0 \n" // R10 holds current cache level << 1
447-
"Loop1: ADD R2, R10, R10, LSR #1 \n" // R2 holds cache "Set" position
448-
" MOV R1, R6, LSR R2 \n" // Bottom 3 bits are the Cache-type for this level
449-
" AND R1, R1, #7 \n" // Isolate those lower 3 bits
450-
" CMP R1, #2 \n"
451-
" BLT Skip \n" // No cache or only instruction cache at this level
452-
453-
" MCR p15, 2, R10, c0, c0, 0 \n" // Write the Cache Size selection register
454-
" ISB \n" // ISB to sync the change to the CacheSizeID reg
455-
" MRC p15, 1, R1, c0, c0, 0 \n" // Reads current Cache Size ID register
456-
" AND R2, R1, #7 \n" // Extract the line length field
457-
" ADD R2, R2, #4 \n" // Add 4 for the line length offset (log2 16 bytes)
458-
" LDR R4, =0x3FF \n"
459-
" ANDS R4, R4, R1, LSR #3 \n" // R4 is the max number on the way size (right aligned)
460-
" CLZ R5, R4 \n" // R5 is the bit position of the way size increment
461-
" LDR R7, =0x7FFF \n"
462-
" ANDS R7, R7, R1, LSR #13 \n" // R7 is the max number of the index size (right aligned)
463-
464-
"Loop2: MOV R9, R4 \n" // R9 working copy of the max way size (right aligned)
465-
466-
"Loop3: ORR R11, R10, R9, LSL R5 \n" // Factor in the Way number and cache number into R11
467-
" ORR R11, R11, R7, LSL R2 \n" // Factor in the Set number
468-
" CMP R0, #0 \n"
469-
" BNE Dccsw \n"
470-
" MCR p15, 0, R11, c7, c6, 2 \n" // DCISW. Invalidate by Set/Way
471-
" B cont \n"
472-
"Dccsw: CMP R0, #1 \n"
473-
" BNE Dccisw \n"
474-
" MCR p15, 0, R11, c7, c10, 2 \n" // DCCSW. Clean by Set/Way
475-
" B cont \n"
476-
"Dccisw: MCR p15, 0, R11, c7, c14, 2 \n" // DCCISW. Clean and Invalidate by Set/Way
477-
"cont: SUBS R9, R9, #1 \n" // Decrement the Way number
478-
" BGE Loop3 \n"
479-
" SUBS R7, R7, #1 \n" // Decrement the Set number
480-
" BGE Loop2 \n"
481-
"Skip: ADD R10, R10, #2 \n" // Increment the cache number
482-
" CMP R3, R10 \n"
483-
" BGT Loop1 \n"
484-
485-
"Finished: \n"
486-
" DSB \n"
487-
" POP {R4-R11} "
488-
);
489-
}
490-
491434
/** \brief Enable Floating Point Unit
492435
493436
Critical section, called from undef handler, so systick is disabled

‎cmsis/TARGET_CORTEX_A/cmsis_compiler.h

Lines changed: 25 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,8 @@
11
/**************************************************************************//**
22
* @file cmsis_compiler.h
33
* @brief CMSIS compiler specific macros, functions, instructions
4-
* @version V1.00
5-
* @date 22. Feb 2017
4+
* @version V1.0.1
5+
* @date 01. December 2017
66
******************************************************************************/
77
/*
88
* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
@@ -54,7 +54,7 @@
5454
#elif defined ( __ICCARM__ )
5555
#include "cmsis_iccarm.h"
5656

57-
57+
5858
/*
5959
* TI ARM Compiler
6060
*/
@@ -70,9 +70,18 @@
7070
#ifndef __STATIC_INLINE
7171
#define __STATIC_INLINE static inline
7272
#endif
73+
#ifndef __STATIC_INLINE
74+
#define __STATIC_INLINE static inline
75+
#endif
76+
#ifndef __STATIC_FORCEINLINE
77+
#define __STATIC_FORCEINLINE __STATIC_INLINE
78+
#endif
7379
#ifndef __NO_RETURN
7480
#define __NO_RETURN __attribute__((noreturn))
7581
#endif
82+
#ifndef __DEPRECATED
83+
#define __DEPRECATED __attribute__((deprecated))
84+
#endif
7685
#ifndef __USED
7786
#define __USED __attribute__((used))
7887
#endif
@@ -110,9 +119,15 @@
110119
#ifndef __STATIC_INLINE
111120
#define __STATIC_INLINE static inline
112121
#endif
122+
#ifndef __STATIC_FORCEINLINE
123+
#define __STATIC_FORCEINLINE __STATIC_INLINE
124+
#endif
113125
#ifndef __NO_RETURN
114126
#define __NO_RETURN __attribute__((noreturn))
115127
#endif
128+
#ifndef __DEPRECATED
129+
#define __DEPRECATED __attribute__((deprecated))
130+
#endif
116131
#ifndef __USED
117132
#define __USED __attribute__((used))
118133
#endif
@@ -146,6 +161,9 @@
146161
#ifndef __STATIC_INLINE
147162
#define __STATIC_INLINE static inline
148163
#endif
164+
#ifndef __STATIC_FORCEINLINE
165+
#define __STATIC_FORCEINLINE __STATIC_INLINE
166+
#endif
149167
#ifndef __NO_RETURN
150168
// NO RETURN is automatically detected hence no warning here
151169
#define __NO_RETURN
@@ -154,6 +172,10 @@
154172
#warning No compiler specific solution for __USED. __USED is ignored.
155173
#define __USED
156174
#endif
175+
#ifndef __DEPRECATED
176+
#warning No compiler specific solution for __DEPRECATED. __DEPRECATED is ignored.
177+
#define __DEPRECATED
178+
#endif
157179
#ifndef __WEAK
158180
#define __WEAK __weak
159181
#endif

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