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Squashed commits from #1002, from Marcomissyou.
Delta target - add RTC, bugfixes in mbed_overrides and pinnames
1 parent dc0b26d commit 331dc07

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5 files changed

+174
-21
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5 files changed

+174
-21
lines changed

‎libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DELTA_DFCM_NNN40/PinNames.h

Lines changed: 15 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -62,7 +62,7 @@ typedef enum {
6262
p28 = NC,
6363
p29 = 29,
6464
p30 = 30,
65-
p31 = 31,
65+
p31 = 31,
6666

6767
LED1 = p7,
6868
LED2 = p13,
@@ -96,19 +96,24 @@ typedef enum {
9696
A3 = p3,
9797
A4 = p4,
9898
A5 = p5,
99-
100-
SWIO = p19,
101-
VERF0 = p0,
99+
100+
SWIO = p19,
101+
VERF0 = p0,
102+
103+
// SPI for controlling internal flash, don't use it.
104+
FLASH_SPIMOSI = 15,
105+
FLASH_SPIMISO = 9,
106+
FLASH_SPICS = 28,
107+
FLASH_SPICLK = 11,
102108
// Not connected
103-
104-
CTS_PIN_NUMBER = NC,
105-
RTS_PIN_NUMBER = NC,
106-
SPI_PSELMOSI1 = NC,
109+
CTS_PIN_NUMBER= NC,
110+
RTS_PIN_NUMBER= NC,
111+
SPI_PSELMOSI1 = NC,
107112
SPI_PSELMISO1 = NC,
108113
SPI_PSELSS1 = NC,
109114
SPI_PSELSCK1 = NC,
110-
LED3 = NC,
111-
LED4 = NC
115+
LED3 = NC,
116+
LED4 = NC
112117
} PinName;
113118

114119
typedef enum {

‎libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DELTA_DFCM_NNN40/device.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -35,7 +35,7 @@
3535

3636
#define DEVICE_CAN 0
3737

38-
#define DEVICE_RTC 0
38+
#define DEVICE_RTC 1
3939

4040
#define DEVICE_ETHERNET 0
4141

‎libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DELTA_DFCM_NNN40/mbed_overrides.c

Lines changed: 87 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -13,9 +13,89 @@
1313
* See the License for the specific language governing permissions and
1414
* limitations under the License.
1515
*/
16-
16+
1717
#include "cmsis.h"
1818

19+
20+
#define SPIM1_SCK_PIN 11u /**< SPI clock GPIO pin number. */
21+
#define SPIM1_MOSI_PIN 15u /**< SPI Master Out Slave In GPIO pin number. */
22+
#define SPIM1_MISO_PIN 9u /**< SPI Master In Slave Out GPIO pin number. */
23+
#define SPIM1_SS_PIN 28u /**< SPI Slave Select GPIO pin number. */
24+
25+
#define CMD_POWER_UP (0xAB)
26+
#define CMD_POWER_DOWN (0xB9)
27+
28+
void spi_flash_init(void)
29+
{
30+
NRF_GPIO->PIN_CNF[SPIM1_MOSI_PIN] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos)
31+
| (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos)
32+
| (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos)
33+
| (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos)
34+
| (GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos);
35+
NRF_GPIO->PIN_CNF[SPIM1_MISO_PIN] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos)
36+
| (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos)
37+
| (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos)
38+
| (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos)
39+
| (GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos);
40+
NRF_GPIO->PIN_CNF[SPIM1_SCK_PIN] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos)
41+
| (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos)
42+
| (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos)
43+
| (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos)
44+
| (GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos);
45+
46+
NRF_GPIO->PIN_CNF[SPIM1_SS_PIN] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos)
47+
| (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos)
48+
| (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos)
49+
| (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos)
50+
| (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
51+
//cs = 1;
52+
NRF_GPIO->OUTSET = (GPIO_OUTSET_PIN28_High << GPIO_OUTSET_PIN28_Pos);
53+
54+
NRF_SPI1->ENABLE = 1;
55+
NRF_SPI1->PSELSCK = SPIM1_SCK_PIN;
56+
NRF_SPI1->PSELMOSI = SPIM1_MISO_PIN;
57+
NRF_SPI1->PSELMISO = SPIM1_MOSI_PIN;
58+
//spi.frequency(1000000);
59+
NRF_SPI1->FREQUENCY = 0x10000000; //1MHz
60+
61+
//spi.format(8,0);
62+
uint32_t config_mode = 0;
63+
config_mode = (SPI_CONFIG_CPHA_Leading << SPI_CONFIG_CPHA_Pos) | (SPI_CONFIG_CPOL_ActiveHigh << SPI_CONFIG_CPOL_Pos); //mode 0
64+
NRF_SPI1->CONFIG = (config_mode | (SPI_CONFIG_ORDER_MsbFirst << SPI_CONFIG_ORDER_Pos));
65+
//cs = 0;
66+
NRF_GPIO->OUTCLR = (GPIO_OUTCLR_PIN28_Clear << GPIO_OUTCLR_PIN28_Pos);
67+
//spi.write(CMD_POWER_UP);
68+
while (!NRF_SPI1->EVENTS_READY == 0) {
69+
}
70+
NRF_SPI1->TXD = (uint32_t)CMD_POWER_UP;
71+
while (!NRF_SPI1->EVENTS_READY == 1) {
72+
}
73+
NRF_SPI1->EVENTS_READY = 0;
74+
NRF_SPI1->RXD;
75+
//wait_ms(30);
76+
// Deselect the device
77+
//cs = 1;
78+
NRF_GPIO->OUTSET = (GPIO_OUTSET_PIN28_High << GPIO_OUTSET_PIN28_Pos);
79+
80+
}
81+
82+
void spi_flash_powerDown(void)
83+
{
84+
NRF_GPIO->OUTCLR = (GPIO_OUTCLR_PIN28_Clear << GPIO_OUTCLR_PIN28_Pos);
85+
//spi.write(CMD_POWER_DOWN);
86+
while (!NRF_SPI1->EVENTS_READY == 0) {
87+
}
88+
NRF_SPI1->TXD = (uint32_t)CMD_POWER_DOWN;
89+
while (!NRF_SPI1->EVENTS_READY == 1) {
90+
}
91+
NRF_SPI1->EVENTS_READY = 0;
92+
NRF_SPI1->RXD;
93+
NRF_GPIO->OUTSET = (GPIO_OUTSET_PIN28_High << GPIO_OUTSET_PIN28_Pos);
94+
95+
//wait for sleep
96+
//wait_us(3);
97+
}
98+
1999
void mbed_sdk_init()
20100
{
21101
// Default SWIO setting, pull SWIO(p19) to low for turning antenna switch to BLE radiated path
@@ -34,4 +114,10 @@ void mbed_sdk_init()
34114
while (NRF_CLOCK->EVENTS_HFCLKSTARTED == 0)
35115
{// Do nothing.
36116
}
117+
118+
spi_flash_init();
119+
120+
//nrf_delay_ms(10);
121+
spi_flash_powerDown();
122+
37123
}

‎libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DELTA_DFCM_NNN40/rtc_api.c

Lines changed: 71 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,71 @@
1+
/* mbed Microcontroller Library
2+
* Copyright (c) 2006-2013 ARM Limited
3+
*
4+
* Licensed under the Apache License, Version 2.0 (the "License");
5+
* you may not use this file except in compliance with the License.
6+
* You may obtain a copy of the License at
7+
*
8+
* http://www.apache.org/licenses/LICENSE-2.0
9+
*
10+
* Unless required by applicable law or agreed to in writing, software
11+
* distributed under the License is distributed on an "AS IS" BASIS,
12+
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13+
* See the License for the specific language governing permissions and
14+
* limitations under the License.
15+
*/
16+
#include "rtc_api.h"
17+
18+
19+
#define LFCLK_FREQUENCY (32768UL)
20+
#define RTC0_COUNTER_PRESCALER ((LFCLK_FREQUENCY/8) - 1)
21+
#define COMPARE_COUNTERTIME (691200UL) //86400 x 8
22+
23+
24+
time_t initTime;
25+
26+
void rtc_init(void) {
27+
28+
NVIC_EnableIRQ(RTC0_IRQn); // Enable Interrupt for the RTC in the core.
29+
//NRF_RTC0->TASKS_STOP =1;
30+
NRF_RTC0->PRESCALER = RTC0_COUNTER_PRESCALER; // Set prescaler to a TICK of RTC_FREQUENCY.
31+
NRF_RTC0->CC[0] = COMPARE_COUNTERTIME; // Compare0 after approx COMPARE_COUNTERTIME seconds.
32+
33+
// Enable COMPARE0 event and COMPARE0 interrupt:
34+
NRF_RTC0->EVTENSET = RTC_EVTENSET_COMPARE0_Msk;
35+
NRF_RTC0->INTENSET = RTC_INTENSET_COMPARE0_Msk;
36+
NRF_RTC0->TASKS_START = 1;
37+
}
38+
39+
void rtc_free(void) {
40+
// [TODO]
41+
}
42+
43+
/*
44+
* Little check routine to see if the RTC has been enabled
45+
*
46+
* Clock Control Register
47+
* RTC_CCR[0] : 0 = Disabled, 1 = Enabled
48+
*
49+
*/
50+
int rtc_isenabled(void) {
51+
// [TODO] return(((NRF_RTC0->TASKS_START) & 0x01) != 0);
52+
}
53+
54+
time_t rtc_read(void) {
55+
56+
time_t t = initTime;
57+
t += (86400*NRF_RTC0->EVENTS_COMPARE[0]);
58+
t += (int)((NRF_RTC0->COUNTER)/8);
59+
return(t);
60+
}
61+
62+
void rtc_write(time_t t) {
63+
// Convert the time in to a tm
64+
65+
// Pause clock, and clear counter register (clears us count)
66+
NRF_RTC0->TASKS_STOP = 1;
67+
68+
initTime = t;
69+
// Restart clock
70+
NRF_RTC0->TASKS_START = 1;
71+
}

‎workspace_tools/targets.py

Lines changed: 0 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -1027,15 +1027,6 @@ def __init__(self):
10271027
self.extra_labels = ['NORDIC', 'MCU_NRF51822', 'MCU_NORDIC_16K', 'DELTA_DFCM_NNN40']
10281028
self.MERGE_SOFT_DEVICE = False
10291029
self.macros += self.common_macros
1030-
1031-
class DELTA_DFCM_NNN40_OTA(NRF51822):
1032-
def __init__(self):
1033-
NRF51822.__init__(self)
1034-
self.core = "Cortex-M0"
1035-
self.extra_labels = ['NORDIC', 'MCU_NRF51822', 'MCU_NORDIC_16K', 'DELTA_DFCM_NNN40']
1036-
self.MERGE_SOFT_DEVICE = False
1037-
self.macros += self.common_macros
1038-
10391030
### ARM ###
10401031

10411032
class ARM_MPS2_M0(Target):

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