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Remove unnecessary peripherals from design files and regenerate source
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144 files changed

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lines changed

‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,9 @@
44
* Description:
55
* Wrapper function to initialize all generated code.
66
* This file was automatically generated and should not be modified.
7-
*
7+
* cfg-backend-cli: 1.2.0.1478
8+
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
9+
*
810
********************************************************************************
911
* Copyright 2017-2019 Cypress Semiconductor Corporation
1012
* SPDX-License-Identifier: Apache-2.0

‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,9 @@
44
* Description:
55
* Simple wrapper header containing all generated files.
66
* This file was automatically generated and should not be modified.
7-
*
7+
* cfg-backend-cli: 1.2.0.1478
8+
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
9+
*
810
********************************************************************************
911
* Copyright 2017-2019 Cypress Semiconductor Corporation
1012
* SPDX-License-Identifier: Apache-2.0

‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,9 @@
44
* Description:
55
* Sentinel file for determining if generated source is up to date.
66
* This file was automatically generated and should not be modified.
7-
*
7+
* cfg-backend-cli: 1.2.0.1478
8+
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
9+
*
810
********************************************************************************
911
* Copyright 2017-2019 Cypress Semiconductor Corporation
1012
* SPDX-License-Identifier: Apache-2.0

‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c

Lines changed: 4 additions & 47 deletions
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,9 @@
44
* Description:
55
* Clock configuration
66
* This file was automatically generated and should not be modified.
7-
*
7+
* cfg-backend-cli: 1.2.0.1478
8+
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
9+
*
810
********************************************************************************
911
* Copyright 2017-2019 Cypress Semiconductor Corporation
1012
* SPDX-License-Identifier: Apache-2.0
@@ -24,22 +26,6 @@
2426

2527
#include "cycfg_clocks.h"
2628

27-
#if defined (CY_USING_HAL)
28-
const cyhal_resource_inst_t CYBSP_UART_CLK_DIV_obj =
29-
{
30-
.type = CYHAL_RSC_CLOCK,
31-
.block_num = CYBSP_UART_CLK_DIV_HW,
32-
.channel_num = CYBSP_UART_CLK_DIV_NUM,
33-
};
34-
#endif //defined (CY_USING_HAL)
35-
#if defined (CY_USING_HAL)
36-
const cyhal_resource_inst_t CYBSP_BT_UART_CLK_DIV_obj =
37-
{
38-
.type = CYHAL_RSC_CLOCK,
39-
.block_num = CYBSP_BT_UART_CLK_DIV_HW,
40-
.channel_num = CYBSP_BT_UART_CLK_DIV_NUM,
41-
};
42-
#endif //defined (CY_USING_HAL)
4329
#if defined (CY_USING_HAL)
4430
const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj =
4531
{
@@ -48,43 +34,14 @@
4834
.channel_num = CYBSP_CSD_CLK_DIV_NUM,
4935
};
5036
#endif //defined (CY_USING_HAL)
51-
#if defined (CY_USING_HAL)
52-
const cyhal_resource_inst_t CYBSP_CSD_COMM_CLK_DIV_obj =
53-
{
54-
.type = CYHAL_RSC_CLOCK,
55-
.block_num = CYBSP_CSD_COMM_CLK_DIV_HW,
56-
.channel_num = CYBSP_CSD_COMM_CLK_DIV_NUM,
57-
};
58-
#endif //defined (CY_USING_HAL)
5937

6038

6139
void init_cycfg_clocks(void)
6240
{
63-
Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_16_BIT, 0U);
64-
Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_16_BIT, 0U, 719U);
65-
Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_16_BIT, 0U);
66-
#if defined (CY_USING_HAL)
67-
cyhal_hwmgr_reserve(&CYBSP_UART_CLK_DIV_obj);
68-
#endif //defined (CY_USING_HAL)
69-
70-
Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_16_BIT, 1U);
71-
Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_16_BIT, 1U, 77U);
72-
Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_16_BIT, 1U);
73-
#if defined (CY_USING_HAL)
74-
cyhal_hwmgr_reserve(&CYBSP_BT_UART_CLK_DIV_obj);
75-
#endif //defined (CY_USING_HAL)
76-
7741
Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 0U);
7842
Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 0U, 0U);
7943
Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 0U);
8044
#if defined (CY_USING_HAL)
81-
cyhal_hwmgr_reserve(&CYBSP_CSD_CLK_DIV_obj);
82-
#endif //defined (CY_USING_HAL)
83-
84-
Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 1U);
85-
Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 1U, 5U);
86-
Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 1U);
87-
#if defined (CY_USING_HAL)
88-
cyhal_hwmgr_reserve(&CYBSP_CSD_COMM_CLK_DIV_obj);
45+
cyhal_hwmgr_reserve(&CYBSP_CSD_CLK_DIV_obj);
8946
#endif //defined (CY_USING_HAL)
9047
}

‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h

Lines changed: 3 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,9 @@
44
* Description:
55
* Clock configuration
66
* This file was automatically generated and should not be modified.
7-
*
7+
* cfg-backend-cli: 1.2.0.1478
8+
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
9+
*
810
********************************************************************************
911
* Copyright 2017-2019 Cypress Semiconductor Corporation
1012
* SPDX-License-Identifier: Apache-2.0
@@ -35,31 +37,13 @@
3537
extern "C" {
3638
#endif
3739

38-
#define CYBSP_UART_CLK_DIV_ENABLED 1U
39-
#define CYBSP_UART_CLK_DIV_HW CY_SYSCLK_DIV_16_BIT
40-
#define CYBSP_UART_CLK_DIV_NUM 0U
41-
#define CYBSP_BT_UART_CLK_DIV_ENABLED 1U
42-
#define CYBSP_BT_UART_CLK_DIV_HW CY_SYSCLK_DIV_16_BIT
43-
#define CYBSP_BT_UART_CLK_DIV_NUM 1U
4440
#define CYBSP_CSD_CLK_DIV_ENABLED 1U
4541
#define CYBSP_CSD_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
4642
#define CYBSP_CSD_CLK_DIV_NUM 0U
47-
#define CYBSP_CSD_COMM_CLK_DIV_ENABLED 1U
48-
#define CYBSP_CSD_COMM_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
49-
#define CYBSP_CSD_COMM_CLK_DIV_NUM 1U
5043

51-
#if defined (CY_USING_HAL)
52-
extern const cyhal_resource_inst_t CYBSP_UART_CLK_DIV_obj;
53-
#endif //defined (CY_USING_HAL)
54-
#if defined (CY_USING_HAL)
55-
extern const cyhal_resource_inst_t CYBSP_BT_UART_CLK_DIV_obj;
56-
#endif //defined (CY_USING_HAL)
5744
#if defined (CY_USING_HAL)
5845
extern const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj;
5946
#endif //defined (CY_USING_HAL)
60-
#if defined (CY_USING_HAL)
61-
extern const cyhal_resource_inst_t CYBSP_CSD_COMM_CLK_DIV_obj;
62-
#endif //defined (CY_USING_HAL)
6347

6448
void init_cycfg_clocks(void);
6549

‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -5,7 +5,9 @@
55
* Contains warnings and errors that occurred while generating code for the
66
* design.
77
* This file was automatically generated and should not be modified.
8-
*
8+
* cfg-backend-cli: 1.2.0.1478
9+
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
10+
*
911
********************************************************************************
1012
* Copyright 2017-2019 Cypress Semiconductor Corporation
1113
* SPDX-License-Identifier: Apache-2.0

‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c

Lines changed: 3 additions & 175 deletions
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,9 @@
44
* Description:
55
* Peripheral Hardware Block configuration
66
* This file was automatically generated and should not be modified.
7-
*
7+
* cfg-backend-cli: 1.2.0.1478
8+
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
9+
*
810
********************************************************************************
911
* Copyright 2017-2019 Cypress Semiconductor Corporation
1012
* SPDX-License-Identifier: Apache-2.0
@@ -24,187 +26,13 @@
2426

2527
#include "cycfg_peripherals.h"
2628

27-
#define CYBSP_USBUART_INTR_LVL_SEL (CY_USBFS_DEV_DRV_SET_SOF_LVL(0x1U) | \
28-
CY_USBFS_DEV_DRV_SET_BUS_RESET_LVL(0x2U) | \
29-
CY_USBFS_DEV_DRV_SET_EP0_LVL(0x2U) | \
30-
CY_USBFS_DEV_DRV_SET_LPM_LVL(0x0U) | \
31-
CY_USBFS_DEV_DRV_SET_ARB_EP_LVL(0x0U) | \
32-
CY_USBFS_DEV_DRV_SET_EP1_LVL(0x1U) | \
33-
CY_USBFS_DEV_DRV_SET_EP2_LVL(0x1U) | \
34-
CY_USBFS_DEV_DRV_SET_EP3_LVL(0x1U) | \
35-
CY_USBFS_DEV_DRV_SET_EP4_LVL(0x1U) | \
36-
CY_USBFS_DEV_DRV_SET_EP5_LVL(0x1U) | \
37-
CY_USBFS_DEV_DRV_SET_EP6_LVL(0x1U) | \
38-
CY_USBFS_DEV_DRV_SET_EP7_LVL(0x1U) | \
39-
CY_USBFS_DEV_DRV_SET_EP8_LVL(0x1U))
40-
4129
cy_stc_csd_context_t cy_csd_0_context =
4230
{
4331
.lockKey = CY_CSD_NONE_KEY,
4432
};
45-
const cy_stc_scb_uart_config_t CYBSP_BT_UART_config =
46-
{
47-
.uartMode = CY_SCB_UART_STANDARD,
48-
.enableMutliProcessorMode = false,
49-
.smartCardRetryOnNack = false,
50-
.irdaInvertRx = false,
51-
.irdaEnableLowPowerReceiver = false,
52-
.oversample = 8,
53-
.enableMsbFirst = false,
54-
.dataWidth = 8UL,
55-
.parity = CY_SCB_UART_PARITY_NONE,
56-
.stopBits = CY_SCB_UART_STOP_BITS_1,
57-
.enableInputFilter = false,
58-
.breakWidth = 11UL,
59-
.dropOnFrameError = false,
60-
.dropOnParityError = false,
61-
.receiverAddress = 0x0UL,
62-
.receiverAddressMask = 0x0UL,
63-
.acceptAddrInFifo = false,
64-
.enableCts = true,
65-
.ctsPolarity = CY_SCB_UART_ACTIVE_LOW,
66-
.rtsRxFifoLevel = 63,
67-
.rtsPolarity = CY_SCB_UART_ACTIVE_LOW,
68-
.rxFifoTriggerLevel = 1UL,
69-
.rxFifoIntEnableMask = 0UL,
70-
.txFifoTriggerLevel = 63UL,
71-
.txFifoIntEnableMask = 0UL,
72-
};
73-
#if defined (CY_USING_HAL)
74-
const cyhal_resource_inst_t CYBSP_BT_UART_obj =
75-
{
76-
.type = CYHAL_RSC_SCB,
77-
.block_num = 2U,
78-
.channel_num = 0U,
79-
};
80-
#endif //defined (CY_USING_HAL)
81-
const cy_stc_scb_ezi2c_config_t CYBSP_CSD_COMM_config =
82-
{
83-
.numberOfAddresses = CY_SCB_EZI2C_ONE_ADDRESS,
84-
.slaveAddress1 = 8U,
85-
.slaveAddress2 = 0U,
86-
.subAddressSize = CY_SCB_EZI2C_SUB_ADDR16_BITS,
87-
.enableWakeFromSleep = false,
88-
};
89-
#if defined (CY_USING_HAL)
90-
const cyhal_resource_inst_t CYBSP_CSD_COMM_obj =
91-
{
92-
.type = CYHAL_RSC_SCB,
93-
.block_num = 3U,
94-
.channel_num = 0U,
95-
};
96-
#endif //defined (CY_USING_HAL)
97-
const cy_stc_smif_config_t CYBSP_QSPI_config =
98-
{
99-
.mode = (uint32_t)CY_SMIF_NORMAL,
100-
.deselectDelay = CYBSP_QSPI_DESELECT_DELAY,
101-
.rxClockSel = (uint32_t)CY_SMIF_SEL_INV_INTERNAL_CLK,
102-
.blockEvent = (uint32_t)CY_SMIF_BUS_ERROR,
103-
};
104-
#if defined (CY_USING_HAL)
105-
const cyhal_resource_inst_t CYBSP_QSPI_obj =
106-
{
107-
.type = CYHAL_RSC_SMIF,
108-
.block_num = 0U,
109-
.channel_num = 0U,
110-
};
111-
#endif //defined (CY_USING_HAL)
112-
const cy_stc_mcwdt_config_t CYBSP_MCWDT_config =
113-
{
114-
.c0Match = 32768U,
115-
.c1Match = 32768U,
116-
.c0Mode = CY_MCWDT_MODE_NONE,
117-
.c1Mode = CY_MCWDT_MODE_NONE,
118-
.c2ToggleBit = 16U,
119-
.c2Mode = CY_MCWDT_MODE_NONE,
120-
.c0ClearOnMatch = false,
121-
.c1ClearOnMatch = false,
122-
.c0c1Cascade = true,
123-
.c1c2Cascade = false,
124-
};
125-
#if defined (CY_USING_HAL)
126-
const cyhal_resource_inst_t CYBSP_MCWDT_obj =
127-
{
128-
.type = CYHAL_RSC_LPTIMER,
129-
.block_num = 0U,
130-
.channel_num = 0U,
131-
};
132-
#endif //defined (CY_USING_HAL)
133-
const cy_stc_rtc_config_t CYBSP_RTC_config =
134-
{
135-
.sec = 0U,
136-
.min = 0U,
137-
.hour = 12U,
138-
.amPm = CY_RTC_AM,
139-
.hrFormat = CY_RTC_24_HOURS,
140-
.dayOfWeek = CY_RTC_SUNDAY,
141-
.date = 1U,
142-
.month = CY_RTC_JANUARY,
143-
.year = 0U,
144-
};
145-
#if defined (CY_USING_HAL)
146-
const cyhal_resource_inst_t CYBSP_RTC_obj =
147-
{
148-
.type = CYHAL_RSC_RTC,
149-
.block_num = 0U,
150-
.channel_num = 0U,
151-
};
152-
#endif //defined (CY_USING_HAL)
153-
const cy_stc_usbfs_dev_drv_config_t CYBSP_USBUART_config =
154-
{
155-
.mode = CY_USBFS_DEV_DRV_EP_MANAGEMENT_CPU,
156-
.epAccess = CY_USBFS_DEV_DRV_USE_8_BITS_DR,
157-
.epBuffer = NULL,
158-
.epBufferSize = 0U,
159-
.dmaConfig[0] = NULL,
160-
.dmaConfig[1] = NULL,
161-
.dmaConfig[2] = NULL,
162-
.dmaConfig[3] = NULL,
163-
.dmaConfig[4] = NULL,
164-
.dmaConfig[5] = NULL,
165-
.dmaConfig[6] = NULL,
166-
.dmaConfig[7] = NULL,
167-
.enableLpm = false,
168-
.intrLevelSel = CYBSP_USBUART_INTR_LVL_SEL,
169-
};
170-
#if defined (CY_USING_HAL)
171-
const cyhal_resource_inst_t CYBSP_USBUART_obj =
172-
{
173-
.type = CYHAL_RSC_USB,
174-
.block_num = 0U,
175-
.channel_num = 0U,
176-
};
177-
#endif //defined (CY_USING_HAL)
17833

17934

18035
void init_cycfg_peripherals(void)
18136
{
18237
Cy_SysClk_PeriphAssignDivider(PCLK_CSD_CLOCK, CY_SYSCLK_DIV_8_BIT, 0U);
183-
184-
Cy_SysClk_PeriphAssignDivider(PCLK_SCB2_CLOCK, CY_SYSCLK_DIV_16_BIT, 1U);
185-
#if defined (CY_USING_HAL)
186-
cyhal_hwmgr_reserve(&CYBSP_BT_UART_obj);
187-
#endif //defined (CY_USING_HAL)
188-
189-
Cy_SysClk_PeriphAssignDivider(PCLK_SCB3_CLOCK, CY_SYSCLK_DIV_8_BIT, 1U);
190-
#if defined (CY_USING_HAL)
191-
cyhal_hwmgr_reserve(&CYBSP_CSD_COMM_obj);
192-
#endif //defined (CY_USING_HAL)
193-
194-
#if defined (CY_USING_HAL)
195-
cyhal_hwmgr_reserve(&CYBSP_QSPI_obj);
196-
#endif //defined (CY_USING_HAL)
197-
198-
#if defined (CY_USING_HAL)
199-
cyhal_hwmgr_reserve(&CYBSP_MCWDT_obj);
200-
#endif //defined (CY_USING_HAL)
201-
202-
#if defined (CY_USING_HAL)
203-
cyhal_hwmgr_reserve(&CYBSP_RTC_obj);
204-
#endif //defined (CY_USING_HAL)
205-
206-
Cy_SysClk_PeriphAssignDivider(PCLK_USB_CLOCK_DEV_BRS, CY_SYSCLK_DIV_16_BIT, 0U);
207-
#if defined (CY_USING_HAL)
208-
cyhal_hwmgr_reserve(&CYBSP_USBUART_obj);
209-
#endif //defined (CY_USING_HAL)
21038
}

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