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[NUC472] Fix CI tests-api-analogin failed
1. Fix UNO pins A5-A7 don't support analog-in by replacing ADC with EADC to implement analog-in HAL. 2. Update CLK driver to fix EADC clock divider setting error. Also fix CLK_Idle() together.
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6 files changed

+277
-152
lines changed

6 files changed

+277
-152
lines changed

‎targets/TARGET_NUVOTON/TARGET_NUC472/TARGET_NUMAKER_PFM_NUC472/PeripheralNames.h

Lines changed: 17 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -44,18 +44,23 @@ typedef enum {
4444
#endif
4545

4646
typedef enum {
47-
ADC_0_0 = (int) NU_MODNAME(ADC_BASE, 0),
48-
ADC_0_1 = (int) NU_MODNAME(ADC_BASE, 1),
49-
ADC_0_2 = (int) NU_MODNAME(ADC_BASE, 2),
50-
ADC_0_3 = (int) NU_MODNAME(ADC_BASE, 3),
51-
ADC_0_4 = (int) NU_MODNAME(ADC_BASE, 4),
52-
ADC_0_5 = (int) NU_MODNAME(ADC_BASE, 5),
53-
ADC_0_6 = (int) NU_MODNAME(ADC_BASE, 6),
54-
ADC_0_7 = (int) NU_MODNAME(ADC_BASE, 7),
55-
ADC_0_8 = (int) NU_MODNAME(ADC_BASE, 8),
56-
ADC_0_9 = (int) NU_MODNAME(ADC_BASE, 9),
57-
ADC_0_10 = (int) NU_MODNAME(ADC_BASE, 10),
58-
ADC_0_11 = (int) NU_MODNAME(ADC_BASE, 11)
47+
ADC_0_0 = (int) NU_MODNAME(EADC_BASE, 0),
48+
ADC_0_1 = (int) NU_MODNAME(EADC_BASE, 1),
49+
ADC_0_2 = (int) NU_MODNAME(EADC_BASE, 2),
50+
ADC_0_3 = (int) NU_MODNAME(EADC_BASE, 3),
51+
ADC_0_4 = (int) NU_MODNAME(EADC_BASE, 4),
52+
ADC_0_5 = (int) NU_MODNAME(EADC_BASE, 5),
53+
ADC_0_6 = (int) NU_MODNAME(EADC_BASE, 6),
54+
ADC_0_7 = (int) NU_MODNAME(EADC_BASE, 7),
55+
56+
ADC_1_0 = (int) NU_MODNAME(EADC_BASE, 8),
57+
ADC_1_1 = (int) NU_MODNAME(EADC_BASE, 9),
58+
ADC_1_2 = (int) NU_MODNAME(EADC_BASE, 10),
59+
ADC_1_3 = (int) NU_MODNAME(EADC_BASE, 11),
60+
ADC_1_4 = (int) NU_MODNAME(EADC_BASE, 12),
61+
ADC_1_5 = (int) NU_MODNAME(EADC_BASE, 13),
62+
ADC_1_6 = (int) NU_MODNAME(EADC_BASE, 14),
63+
ADC_1_7 = (int) NU_MODNAME(EADC_BASE, 15),
5964
} ADCName;
6065

6166
typedef enum {

‎targets/TARGET_NUVOTON/TARGET_NUC472/TARGET_NUMAKER_PFM_NUC472/PeripheralPins.c

Lines changed: 8 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -210,10 +210,14 @@ const PinMap PinMap_ADC[] = {
210210
{PE_6, ADC_0_6, SYS_GPE_MFPL_PE6MFP_ADC0_6}, // ADC0_6
211211
{PE_7, ADC_0_7, SYS_GPE_MFPL_PE7MFP_ADC0_7}, // ADC0_7
212212

213-
{PE_8, ADC_0_8, SYS_GPE_MFPH_PE8MFP_ADC1_0}, // ADC0_8/ADC1_0
214-
{PE_9, ADC_0_9, SYS_GPE_MFPH_PE9MFP_ADC1_1}, // ADC0_9/ADC1_1
215-
{PE_10, ADC_0_10, SYS_GPE_MFPH_PE10MFP_ADC1_2}, // ADC0_10/ADC1_2
216-
{PE_11, ADC_0_11, SYS_GPE_MFPH_PE11MFP_ADC1_3}, // ADC0_11/ADC1_3
213+
{PE_8, ADC_1_0, SYS_GPE_MFPH_PE8MFP_ADC1_0}, // ADC1_0
214+
{PE_9, ADC_1_1, SYS_GPE_MFPH_PE9MFP_ADC1_1}, // ADC1_1
215+
{PE_10, ADC_1_2, SYS_GPE_MFPH_PE10MFP_ADC1_2}, // ADC1_2
216+
{PE_11, ADC_1_3, SYS_GPE_MFPH_PE11MFP_ADC1_3}, // ADC1_3
217+
{PE_12, ADC_1_4, SYS_GPE_MFPH_PE12MFP_ADC1_4}, // ADC1_4
218+
{PE_13, ADC_1_5, SYS_GPE_MFPH_PE13MFP_ADC1_5}, // ADC1_5
219+
{PE_14, ADC_1_6, SYS_GPE_MFPH_PE14MFP_ADC1_6}, // ADC1_6
220+
{PE_15, ADC_1_7, SYS_GPE_MFPH_PE15MFP_ADC1_7}, // ADC1_7
217221

218222
{NC, NC, 0}
219223
};

‎targets/TARGET_NUVOTON/TARGET_NUC472/TARGET_NUMAKER_PFM_NUC472/mbed_overrides.c

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -77,6 +77,8 @@ void mbed_sdk_init(void)
7777
#if DEVICE_ANALOGIN
7878
/* Vref connect to AVDD */
7979
SYS->VREFCTL = (SYS->VREFCTL & ~SYS_VREFCTL_VREFCTL_Msk) | SYS_VREFCTL_VREF_AVDD;
80+
/* Switch ADC0 to EADC mode */
81+
SYS->VREFCTL = (SYS->VREFCTL & ~SYS_VREFCTL_ADCMODESEL_Msk) | SYS_VREFCTL_ADCMODESEL_EADC;
8082
#endif
8183

8284
/* Update System Core Clock */

‎targets/TARGET_NUVOTON/TARGET_NUC472/analogin_api.c

Lines changed: 30 additions & 66 deletions
Original file line numberDiff line numberDiff line change
@@ -23,60 +23,26 @@
2323
#include "PeripheralPins.h"
2424
#include "nu_modutil.h"
2525

26-
struct nu_adc_var {
27-
uint32_t en_msk;
28-
};
29-
30-
static struct nu_adc_var adc0_var = {
31-
.en_msk = 0
32-
};
33-
static struct nu_adc_var adc1_var = {
34-
.en_msk = 0
35-
};
36-
static struct nu_adc_var adc2_var = {
37-
.en_msk = 0
38-
};
39-
static struct nu_adc_var adc3_var = {
40-
.en_msk = 0
41-
};
42-
static struct nu_adc_var adc4_var = {
43-
.en_msk = 0
44-
};
45-
static struct nu_adc_var adc5_var = {
46-
.en_msk = 0
47-
};
48-
static struct nu_adc_var adc6_var = {
49-
.en_msk = 0
50-
};
51-
static struct nu_adc_var adc7_var = {
52-
.en_msk = 0
53-
};
54-
static struct nu_adc_var adc8_var = {
55-
.en_msk = 0
56-
};
57-
static struct nu_adc_var adc9_var = {
58-
.en_msk = 0
59-
};
60-
static struct nu_adc_var adc10_var = {
61-
.en_msk = 0
62-
};
63-
static struct nu_adc_var adc11_var = {
64-
.en_msk = 0
65-
};
26+
static uint32_t adc_modinit_mask = 0;
6627

6728
static const struct nu_modinit_s adc_modinit_tab[] = {
68-
{ADC_0_0, ADC_MODULE, CLK_CLKSEL1_ADCSEL_HIRC, CLK_CLKDIV0_ADC(1), ADC_RST, ADC_IRQn, &adc0_var},
69-
{ADC_0_1, ADC_MODULE, CLK_CLKSEL1_ADCSEL_HIRC, CLK_CLKDIV0_ADC(1), ADC_RST, ADC_IRQn, &adc1_var},
70-
{ADC_0_2, ADC_MODULE, CLK_CLKSEL1_ADCSEL_HIRC, CLK_CLKDIV0_ADC(1), ADC_RST, ADC_IRQn, &adc2_var},
71-
{ADC_0_3, ADC_MODULE, CLK_CLKSEL1_ADCSEL_HIRC, CLK_CLKDIV0_ADC(1), ADC_RST, ADC_IRQn, &adc3_var},
72-
{ADC_0_4, ADC_MODULE, CLK_CLKSEL1_ADCSEL_HIRC, CLK_CLKDIV0_ADC(1), ADC_RST, ADC_IRQn, &adc4_var},
73-
{ADC_0_5, ADC_MODULE, CLK_CLKSEL1_ADCSEL_HIRC, CLK_CLKDIV0_ADC(1), ADC_RST, ADC_IRQn, &adc5_var},
74-
{ADC_0_6, ADC_MODULE, CLK_CLKSEL1_ADCSEL_HIRC, CLK_CLKDIV0_ADC(1), ADC_RST, ADC_IRQn, &adc6_var},
75-
{ADC_0_7, ADC_MODULE, CLK_CLKSEL1_ADCSEL_HIRC, CLK_CLKDIV0_ADC(1), ADC_RST, ADC_IRQn, &adc7_var},
76-
{ADC_0_8, ADC_MODULE, CLK_CLKSEL1_ADCSEL_HIRC, CLK_CLKDIV0_ADC(1), ADC_RST, ADC_IRQn, &adc8_var},
77-
{ADC_0_9, ADC_MODULE, CLK_CLKSEL1_ADCSEL_HIRC, CLK_CLKDIV0_ADC(1), ADC_RST, ADC_IRQn, &adc9_var},
78-
{ADC_0_10, ADC_MODULE, CLK_CLKSEL1_ADCSEL_HIRC, CLK_CLKDIV0_ADC(1), ADC_RST, ADC_IRQn, &adc10_var},
79-
{ADC_0_11, ADC_MODULE, CLK_CLKSEL1_ADCSEL_HIRC, CLK_CLKDIV0_ADC(1), ADC_RST, ADC_IRQn, &adc11_var}
29+
{ADC_0_0, EADC_MODULE, CLK_CLKSEL1_ADCSEL_PLL, CLK_CLKDIV0_ADC(5), ADC_RST, EADC0_IRQn, NULL},
30+
{ADC_0_1, EADC_MODULE, CLK_CLKSEL1_ADCSEL_PLL, CLK_CLKDIV0_ADC(5), ADC_RST, EADC0_IRQn, NULL},
31+
{ADC_0_2, EADC_MODULE, CLK_CLKSEL1_ADCSEL_PLL, CLK_CLKDIV0_ADC(5), ADC_RST, EADC0_IRQn, NULL},
32+
{ADC_0_3, EADC_MODULE, CLK_CLKSEL1_ADCSEL_PLL, CLK_CLKDIV0_ADC(5), ADC_RST, EADC0_IRQn, NULL},
33+
{ADC_0_4, EADC_MODULE, CLK_CLKSEL1_ADCSEL_PLL, CLK_CLKDIV0_ADC(5), ADC_RST, EADC0_IRQn, NULL},
34+
{ADC_0_5, EADC_MODULE, CLK_CLKSEL1_ADCSEL_PLL, CLK_CLKDIV0_ADC(5), ADC_RST, EADC0_IRQn, NULL},
35+
{ADC_0_6, EADC_MODULE, CLK_CLKSEL1_ADCSEL_PLL, CLK_CLKDIV0_ADC(5), ADC_RST, EADC0_IRQn, NULL},
36+
{ADC_0_7, EADC_MODULE, CLK_CLKSEL1_ADCSEL_PLL, CLK_CLKDIV0_ADC(5), ADC_RST, EADC0_IRQn, NULL},
37+
38+
{ADC_1_0, EADC_MODULE, CLK_CLKSEL1_ADCSEL_PLL, CLK_CLKDIV0_ADC(5), ADC_RST, EADC0_IRQn, NULL},
39+
{ADC_1_1, EADC_MODULE, CLK_CLKSEL1_ADCSEL_PLL, CLK_CLKDIV0_ADC(5), ADC_RST, EADC0_IRQn, NULL},
40+
{ADC_1_2, EADC_MODULE, CLK_CLKSEL1_ADCSEL_PLL, CLK_CLKDIV0_ADC(5), ADC_RST, EADC0_IRQn, NULL},
41+
{ADC_1_3, EADC_MODULE, CLK_CLKSEL1_ADCSEL_PLL, CLK_CLKDIV0_ADC(5), ADC_RST, EADC0_IRQn, NULL},
42+
{ADC_1_4, EADC_MODULE, CLK_CLKSEL1_ADCSEL_PLL, CLK_CLKDIV0_ADC(5), ADC_RST, EADC0_IRQn, NULL},
43+
{ADC_1_5, EADC_MODULE, CLK_CLKSEL1_ADCSEL_PLL, CLK_CLKDIV0_ADC(5), ADC_RST, EADC0_IRQn, NULL},
44+
{ADC_1_6, EADC_MODULE, CLK_CLKSEL1_ADCSEL_PLL, CLK_CLKDIV0_ADC(5), ADC_RST, EADC0_IRQn, NULL},
45+
{ADC_1_7, EADC_MODULE, CLK_CLKSEL1_ADCSEL_PLL, CLK_CLKDIV0_ADC(5), ADC_RST, EADC0_IRQn, NULL}
8046
};
8147

8248
void analogin_init(analogin_t *obj, PinName pin)
@@ -88,8 +54,10 @@ void analogin_init(analogin_t *obj, PinName pin)
8854
MBED_ASSERT(modinit != NULL);
8955
MBED_ASSERT(modinit->modname == obj->adc);
9056

57+
EADC_T *eadc_base = (EADC_T *) NU_MODBASE(obj->adc);
58+
9159
// NOTE: All channels (identified by ADCName) share a ADC module. This reset will also affect other channels of the same ADC module.
92-
if (! ((struct nu_adc_var *) modinit->var)->en_msk) {
60+
if (! adc_modinit_mask) {
9361
// Reset this module if no channel enabled
9462
SYS_ResetModule(modinit->rsetidx);
9563

@@ -98,33 +66,29 @@ void analogin_init(analogin_t *obj, PinName pin)
9866
// Enable clock of paired channels
9967
CLK_EnableModuleClock(modinit->clkidx);
10068

101-
// Power on ADC
102-
ADC_POWER_ON(ADC);
69+
// Make EADC_module ready to convert
70+
EADC_Open(eadc_base, 0);
10371
}
10472

105-
ADC_T *adc_base = (ADC_T *) NU_MODBASE(obj->adc);
10673
uint32_t chn = NU_MODSUBINDEX(obj->adc);
10774

10875
// Wire pinout
10976
pinmap_pinout(pin, PinMap_ADC);
11077

111-
// Enable channel 0
112-
ADC_Open(adc_base,
113-
ADC_INPUT_MODE_SINGLE_END,
114-
ADC_OPERATION_MODE_SINGLE,
115-
1 << chn); // ADC_CH_0_MASK~ADC_CH_11_MASK
78+
// Configure the sample module Nmod for analog input channel Nch and software trigger source
79+
EADC_ConfigSampleModule(eadc_base, chn, EADC_SOFTWARE_TRIGGER, chn % 8);
11680

117-
((struct nu_adc_var *) modinit->var)->en_msk |= 1 << chn;
81+
adc_modinit_mask |= 1 << chn;
11882
}
11983

12084
uint16_t analogin_read_u16(analogin_t *obj)
12185
{
122-
ADC_T *adc_base = (ADC_T *) NU_MODBASE(obj->adc);
86+
EADC_T *eadc_base = (EADC_T *) NU_MODBASE(obj->adc);
12387
uint32_t chn = NU_MODSUBINDEX(obj->adc);
12488

125-
ADC_START_CONV(adc_base);
126-
while (adc_base->CTL & ADC_CTL_SWTRG_Msk);
127-
uint16_t conv_res_12 = ADC_GET_CONVERSION_DATA(adc_base, chn);
89+
EADC_START_CONV(eadc_base, 1 << chn);
90+
while (EADC_GET_DATA_VALID_FLAG(eadc_base, 1 << chn) != (1 << chn));
91+
uint16_t conv_res_12 = EADC_GET_CONV_DATA(eadc_base, chn);
12892
// Just 12 bits are effective. Convert to 16 bits.
12993
// conv_res_12: 0000 b11b10b9b8 b7b6b5b4 b3b2b1b0
13094
// conv_res_16: b11b10b9b8 b7b6b5b4 b3b2b1b0 b11b10b9b8

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