@@ -48,12 +48,21 @@ static void powerdown_nvic()
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int i ;
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int j ;
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+ #if defined(__CORTEX_M23 )
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+ // M23 doesn't support ICTR and supports up to 240 external interrupts.
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+ isr_groups_32 = 8 ;
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+ #else
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isr_groups_32 = ((SCnSCB -> ICTR & SCnSCB_ICTR_INTLINESNUM_Msk ) >> SCnSCB_ICTR_INTLINESNUM_Pos ) + 1 ;
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+ #endif
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for (i = 0 ; i < isr_groups_32 ; i ++ ) {
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NVIC -> ICER [i ] = 0xFFFFFFFF ;
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NVIC -> ICPR [i ] = 0xFFFFFFFF ;
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for (j = 0 ; j < 8 ; j ++ ) {
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+ #if defined(__CORTEX_M23 )
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+ NVIC -> IPR [i * 8 + j ] = 0x00000000 ;
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+ #else
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NVIC -> IP [i * 8 + j ] = 0x00000000 ;
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+ #endif
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}
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}
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}
@@ -68,18 +77,27 @@ static void powerdown_scb(uint32_t vtor)
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SCB -> AIRCR = 0x05FA | 0x0000 ;
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SCB -> SCR = 0x00000000 ;
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// SCB->CCR - Implementation defined value
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+ #if defined(__CORTEX_M23 )
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+ for (i = 0 ; i < 2 ; i ++ ) {
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+ SCB -> SHPR [i ] = 0x00 ;
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+ }
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+ #else
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for (i = 0 ; i < 12 ; i ++ ) {
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#if defined(__CORTEX_M7 )
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SCB -> SHPR [i ] = 0x00 ;
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#else
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SCB -> SHP [i ] = 0x00 ;
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#endif
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}
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+ #endif
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SCB -> SHCSR = 0x00000000 ;
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+ #if defined(__CORTEX_M23 )
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+ #else
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SCB -> CFSR = 0xFFFFFFFF ;
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SCB -> HFSR = SCB_HFSR_DEBUGEVT_Msk | SCB_HFSR_FORCED_Msk | SCB_HFSR_VECTTBL_Msk ;
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SCB -> DFSR = SCB_DFSR_EXTERNAL_Msk | SCB_DFSR_VCATCH_Msk |
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SCB_DFSR_DWTTRAP_Msk | SCB_DFSR_BKPT_Msk | SCB_DFSR_HALTED_Msk ;
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+ #endif
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// SCB->MMFAR - Implementation defined value
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// SCB->BFAR - Implementation defined value
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// SCB->AFSR - Implementation defined value
@@ -107,7 +125,9 @@ __asm static void start_new_application(void *sp, void *pc)
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void start_new_application (void * sp , void * pc )
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{
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__asm volatile (
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- "mov r2 , #0 \n "
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+ "movw r2, #0 \n" // Fail to compile "mov r2, #0" with ARMC6. Replace with MOVW.
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+ // We needn't "movt r2, #0" immediately following because MOVW
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+ // will zero-extend the 16-bit immediate.
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"msr control, r2 \n" // Switch to main stack
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"mov sp, %0 \n"
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"msr primask, r2 \n" // Enable interrupts
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