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Merge pull request #10587 from d-kato/ca9_armc6
GR_LYCHEE,RZ_A1H,VK_RZ_A1H: Fix greentea test failure with ARMC6
2 parents c4b32cd + 14150bb commit 3e1a24b

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7 files changed

+47
-42
lines changed

7 files changed

+47
-42
lines changed

‎cmsis/TARGET_CORTEX_A/cmsis_armcc.h

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1,11 +1,11 @@
11
/**************************************************************************//**
22
* @file cmsis_armcc.h
33
* @brief CMSIS compiler specific macros, functions, instructions
4-
* @version V1.0.2
5-
* @date 10. January 2018
4+
* @version V1.0.3
5+
* @date 15. May 2019
66
******************************************************************************/
77
/*
8-
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
8+
* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
99
*
1010
* SPDX-License-Identifier: Apache-2.0
1111
*
@@ -533,10 +533,10 @@ __STATIC_INLINE __ASM void __FPU_Enable(void)
533533
ENDIF
534534

535535
//Initialise FPSCR to a known state
536-
VMRS R2,FPSCR
537-
LDR R3,=0x00086060 //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
538-
AND R2,R2,R3
539-
VMSR FPSCR,R2
536+
VMRS R1,FPSCR
537+
LDR R2,=0x00086060 //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
538+
AND R1,R1,R2
539+
VMSR FPSCR,R1
540540

541541
BX LR
542542
}

‎cmsis/TARGET_CORTEX_A/cmsis_armclang.h

Lines changed: 7 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,8 @@
11
/**************************************************************************//**
22
* @file cmsis_armclang.h
33
* @brief CMSIS compiler specific macros, functions, instructions
4-
* @version V1.1.0
5-
* @date 18. March 2019
4+
* @version V1.1.1
5+
* @date 15. May 2019
66
******************************************************************************/
77
/*
88
* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
@@ -509,10 +509,11 @@ __STATIC_INLINE void __FPU_Enable(void)
509509
#endif
510510

511511
//Initialise FPSCR to a known state
512-
" VMRS R2,FPSCR \n"
513-
" LDR R3,=0x00086060 \n" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
514-
" AND R2,R2,R3 \n"
515-
" VMSR FPSCR,R2 "
512+
" VMRS R1,FPSCR \n"
513+
" LDR R2,=0x00086060 \n" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
514+
" AND R1,R1,R2 \n"
515+
" VMSR FPSCR,R1 "
516+
: : : "cc", "r1", "r2"
516517
);
517518
}
518519

‎cmsis/TARGET_CORTEX_A/cmsis_gcc.h

Lines changed: 8 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1,11 +1,11 @@
11
/**************************************************************************//**
22
* @file cmsis_gcc.h
33
* @brief CMSIS compiler specific macros, functions, instructions
4-
* @version V1.1.0
5-
* @date 20. December 2018
4+
* @version V1.1.1
5+
* @date 15. May 2019
66
******************************************************************************/
77
/*
8-
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
8+
* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
99
*
1010
* SPDX-License-Identifier: Apache-2.0
1111
*
@@ -683,10 +683,11 @@ __STATIC_INLINE void __FPU_Enable(void)
683683
#endif
684684

685685
//Initialise FPSCR to a known state
686-
" VMRS R2,FPSCR \n"
687-
" LDR R3,=0x00086060 \n" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
688-
" AND R2,R2,R3 \n"
689-
" VMSR FPSCR,R2 "
686+
" VMRS R1,FPSCR \n"
687+
" LDR R2,=0x00086060 \n" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
688+
" AND R1,R1,R2 \n"
689+
" VMSR FPSCR,R1 "
690+
: : : "cc", "r1", "r2"
690691
);
691692
}
692693

‎cmsis/TARGET_CORTEX_A/cmsis_iccarm.h

Lines changed: 8 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -2,12 +2,13 @@
22
* @file cmsis_iccarm.h
33
* @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file
44
* @version V5.0.7
5-
* @date 04. Semptember 2018
5+
* @date 15. May 2019
66
******************************************************************************/
77

88
//------------------------------------------------------------------------------
99
//
1010
// Copyright (c) 2017-2018 IAR Systems
11+
// Copyright (c) 2018-2019 Arm Limited
1112
//
1213
// Licensed under the Apache License, Version 2.0 (the "License")
1314
// you may not use this file except in compliance with the License.
@@ -547,10 +548,12 @@ void __FPU_Enable(void)
547548
#endif
548549

549550
//Initialise FPSCR to a known state
550-
" VMRS R2,FPSCR \n"
551-
" MOV32 R3,#0x00086060 \n" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
552-
" AND R2,R2,R3 \n"
553-
" VMSR FPSCR,R2 \n");
551+
" VMRS R1,FPSCR \n"
552+
" MOV32 R2,#0x00086060 \n" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
553+
" AND R1,R1,R2 \n"
554+
" VMSR FPSCR,R1 \n"
555+
: : : "cc", "r1", "r2"
556+
);
554557
}
555558

556559

‎targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/system_RZ_A1LU.c

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -91,7 +91,12 @@ void SystemInit (void)
9191
{
9292
/* do not use global variables because this function is called before
9393
reaching pre-main. RW section may be overwritten afterwards. */
94-
94+
95+
#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
96+
// Enable FPU
97+
__FPU_Enable();
98+
#endif
99+
95100
// Enable SRAM write access
96101
CPG.SYSCR3 = 0x0F;
97102

@@ -130,11 +135,6 @@ void SystemInit (void)
130135
L2C_Enable();
131136
#endif
132137

133-
#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
134-
// Enable FPU
135-
__FPU_Enable();
136-
#endif
137-
138138
// IRQ Initialize
139139
IRQ_Initialize();
140140
}

‎targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/system_RZ_A1H.c

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -91,7 +91,12 @@ void SystemInit (void)
9191
{
9292
/* do not use global variables because this function is called before
9393
reaching pre-main. RW section may be overwritten afterwards. */
94-
94+
95+
#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
96+
// Enable FPU
97+
__FPU_Enable();
98+
#endif
99+
95100
// Enable SRAM write access
96101
CPG.SYSCR3 = 0x0F;
97102

@@ -130,11 +135,6 @@ void SystemInit (void)
130135
L2C_Enable();
131136
#endif
132137

133-
#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
134-
// Enable FPU
135-
__FPU_Enable();
136-
#endif
137-
138138
// IRQ Initialize
139139
IRQ_Initialize();
140140
}

‎targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/system_VK_RZ_A1H.c

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -92,6 +92,11 @@ void SystemInit (void)
9292
/* do not use global variables because this function is called before
9393
reaching pre-main. RW section maybe overwritten afterwards. */
9494

95+
#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
96+
// Enable FPU
97+
__FPU_Enable();
98+
#endif
99+
95100
// Enable SRAM write access
96101
CPG.SYSCR3 = 0x0F;
97102

@@ -130,11 +135,6 @@ void SystemInit (void)
130135
L2C_Enable();
131136
#endif
132137

133-
#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
134-
// Enable FPU
135-
__FPU_Enable();
136-
#endif
137-
138138
// IRQ Initialize
139139
IRQ_Initialize();
140140
}

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