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dave-wudave-wu
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Cleaned up some formatting issues.
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  • targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api

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‎targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/us_ticker.c

Lines changed: 85 additions & 84 deletions
Original file line numberDiff line numberDiff line change
@@ -76,136 +76,137 @@ static ADI_TMR_TypeDef * adi_tmr_registers[ADI_TMR_DEVICE_NUM] = {pADI_TMR0, pAD
7676
*---------------------------------------------------------------------------*/
7777
static void GP1CallbackFunction(void *pCBParam, uint32_t Event, void * pArg)
7878
{
79-
Upper_count++;
79+
Upper_count++;
8080
}
8181

8282

8383
static uint32_t get_current_time(void)
8484
{
85-
uint16_t tmrcnt0, tmrcnt1;
86-
uint32_t totaltmr0, totaltmr1;
87-
uint32_t uc1, tmrpend0, tmrpend1;
85+
uint16_t tmrcnt0, tmrcnt1;
86+
uint32_t totaltmr0, totaltmr1;
87+
uint32_t uc1, tmrpend0, tmrpend1;
8888

8989
do {
90-
volatile uint32_t *ucptr = &Upper_count;
91-
92-
/*
93-
* Carefully coded to prevent race conditions. Do not make changes unless you understand all the
94-
* implications.
95-
*
96-
* Note this function can be called with interrupts globally disabled or enabled. It has been coded to work in both cases.
97-
*
98-
* TMR0 and TMR1 both run from the same synchronous clock. TMR0 runs at 26MHz and TMR1 runs at 26/256MHz.
99-
* TMR1 generates an interrupt every time it overflows its 16 bit counter. TMR0 runs faster and provides
100-
* the lowest 8 bits of the current time count. When TMR0 and TMR1 are combined, they provide 24 bits of
101-
* timer precision. i.e. (TMR0.CURCNT & 0xff) + (TMR1.CURCNT << 8)
102-
*
103-
* There are several race conditions protected against:
104-
* 1. TMR0 and TMR1 are both read at the same time, however, on rare occasions, one will have incremented before the other.
105-
* Therefore we read both timer counters, and check if the middle 8 bits match, if they don't then read the counts again
106-
* until they do. This ensures that one or the other counters are stable with respect to each other.
107-
*
108-
* 2. TMR1.CURCNT and Upper_count racing. Prevent this by disabling the TMR1 interrupt, which stops Upper_count increment interrupt (GP1CallbackFunction).
109-
* Then check pending bit of TMR1 to see if we missed Upper_count interrupt, and add it manually later.
110-
*
111-
* 3. Race between the TMR1 pend, and the TMR1.CURCNT read. Even with TMR1 interrupt disabled, the pend bit
112-
* may be set while TMR1.CURCNT is being read. We don't know if the pend bit matches the TMR1 state.
113-
* To prevent this, the pending bit is read twice, and we see if it matches; if it doesn't, loop around again.
114-
*
115-
* Note the TMR1 interrupt is enabled on each iteration of the loop to flush out any pending TMR1 interrupt,
116-
* thereby clearing any TMR1 pend's. This have no effect if this routine is called with interrupts globally disabled.
117-
*/
118-
119-
NVIC_DisableIRQ(adi_tmr_interrupt[ADI_TMR_DEVICE_GP1]); // Prevent Upper_count increment
120-
tmrpend0 = NVIC_GetPendingIRQ(adi_tmr_interrupt[ADI_TMR_DEVICE_GP1]);
121-
// Check if there is a pending interrupt for timer 1
90+
volatile uint32_t *ucptr = &Upper_count;
91+
92+
/*
93+
* Carefully coded to prevent race conditions. Do not make changes unless you understand all the
94+
* implications.
95+
*
96+
* Note this function can be called with interrupts globally disabled or enabled. It has been coded to work in both cases.
97+
*
98+
* TMR0 and TMR1 both run from the same synchronous clock. TMR0 runs at 26MHz and TMR1 runs at 26/256MHz.
99+
* TMR1 generates an interrupt every time it overflows its 16 bit counter. TMR0 runs faster and provides
100+
* the lowest 8 bits of the current time count. When TMR0 and TMR1 are combined, they provide 24 bits of
101+
* timer precision. i.e. (TMR0.CURCNT & 0xff) + (TMR1.CURCNT << 8)
102+
*
103+
* There are several race conditions protected against:
104+
* 1. TMR0 and TMR1 are both read at the same time, however, on rare occasions, one will have incremented before the other.
105+
* Therefore we read both timer counters, and check if the middle 8 bits match, if they don't then read the counts again
106+
* until they do. This ensures that one or the other counters are stable with respect to each other.
107+
*
108+
* 2. TMR1.CURCNT and Upper_count racing. Prevent this by disabling the TMR1 interrupt, which stops Upper_count increment interrupt (GP1CallbackFunction).
109+
* Then check pending bit of TMR1 to see if we missed Upper_count interrupt, and add it manually later.
110+
*
111+
* 3. Race between the TMR1 pend, and the TMR1.CURCNT read. Even with TMR1 interrupt disabled, the pend bit
112+
* may be set while TMR1.CURCNT is being read. We don't know if the pend bit matches the TMR1 state.
113+
* To prevent this, the pending bit is read twice, and we see if it matches; if it doesn't, loop around again.
114+
*
115+
* Note the TMR1 interrupt is enabled on each iteration of the loop to flush out any pending TMR1 interrupt,
116+
* thereby clearing any TMR1 pend's. This have no effect if this routine is called with interrupts globally disabled.
117+
*/
118+
119+
NVIC_DisableIRQ(adi_tmr_interrupt[ADI_TMR_DEVICE_GP1]); // Prevent Upper_count increment
120+
tmrpend0 = NVIC_GetPendingIRQ(adi_tmr_interrupt[ADI_TMR_DEVICE_GP1]);
121+
// Check if there is a pending interrupt for timer 1
122122

123123
__DMB(); // memory barrier: read GP0 before GP1
124124

125-
tmrcnt0 = adi_tmr_registers[ADI_TMR_DEVICE_GP0]->CURCNT; // to minimize skew, read both timers manually
125+
tmrcnt0 = adi_tmr_registers[ADI_TMR_DEVICE_GP0]->CURCNT; // to minimize skew, read both timers manually
126126

127-
__DMB(); // memory barrier: read GP0 before GP1
127+
__DMB(); // memory barrier: read GP0 before GP1
128128

129-
tmrcnt1 = adi_tmr_registers[ADI_TMR_DEVICE_GP1]->CURCNT; // read both timers manually
129+
tmrcnt1 = adi_tmr_registers[ADI_TMR_DEVICE_GP1]->CURCNT; // read both timers manually
130130

131-
totaltmr0 = tmrcnt0; // expand to u32 bits
132-
totaltmr1 = tmrcnt1; // expand to u32 bits
131+
totaltmr0 = tmrcnt0; // expand to u32 bits
132+
totaltmr1 = tmrcnt1; // expand to u32 bits
133133

134-
tmrcnt0 &= 0xff00u;
135-
tmrcnt1 <<= 8;
134+
tmrcnt0 &= 0xff00u;
135+
tmrcnt1 <<= 8;
136136

137137
__DMB();
138138

139-
uc1 = *ucptr; // Read Upper_count
139+
uc1 = *ucptr; // Read Upper_count
140140

141-
tmrpend1 = NVIC_GetPendingIRQ(adi_tmr_interrupt[ADI_TMR_DEVICE_GP1]);
142-
// Check for a pending interrupt again. Only leave loop if they match
141+
tmrpend1 = NVIC_GetPendingIRQ(adi_tmr_interrupt[ADI_TMR_DEVICE_GP1]);
142+
// Check for a pending interrupt again. Only leave loop if they match
143143

144-
NVIC_EnableIRQ(adi_tmr_interrupt[ADI_TMR_DEVICE_GP1]); // enable interrupt on every loop to allow TMR1 interrupt to run
144+
NVIC_EnableIRQ(adi_tmr_interrupt[ADI_TMR_DEVICE_GP1]); // enable interrupt on every loop to allow TMR1 interrupt to run
145145
} while ((tmrcnt0 != tmrcnt1) || (tmrpend0 != tmrpend1));
146146

147-
totaltmr1 <<= 8; // Timer1 runs 256x slower
148-
totaltmr1 += totaltmr0 & 0xffu; // Use last 8 bits of Timer0 as it runs faster
149-
// totaltmr1 now contain 24 bits of significance
147+
totaltmr1 <<= 8; // Timer1 runs 256x slower
148+
totaltmr1 += totaltmr0 & 0xffu; // Use last 8 bits of Timer0 as it runs faster
149+
// totaltmr1 now contain 24 bits of significance
150150

151-
if (tmrpend0) { // If an interrupt is pending, then increment local copy of upper count
152-
uc1++;
153-
}
151+
if (tmrpend0) { // If an interrupt is pending, then increment local copy of upper count
152+
uc1++;
153+
}
154154

155-
uint64_t Uc = totaltmr1; // expand out to 64 bits unsigned
156-
Uc += ((uint64_t) uc1) << 24; // Add on the upper count to get the full precision count
155+
uint64_t Uc = totaltmr1; // expand out to 64 bits unsigned
156+
Uc += ((uint64_t) uc1) << 24; // Add on the upper count to get the full precision count
157157

158-
// Divide Uc by 26 (26MHz converted to 1MHz) todo scale for other clock freqs
158+
// Divide Uc by 26 (26MHz converted to 1MHz) todo scale for other clock freqs
159159

160-
Uc *= 1290555u; // Divide total(1/26) << 25
161-
Uc >>= 25; // shift back. Fixed point avoid use of floating point divide.
162-
// Compiler does this inline using shifts and adds.
160+
Uc *= 1290555u; // Divide total(1/26) << 25
161+
Uc >>= 25; // shift back. Fixed point avoid use of floating point divide.
162+
// Compiler does this inline using shifts and adds.
163163

164-
return Uc;
164+
return Uc;
165165
}
166166

167167

168168
static void calc_event_counts(uint32_t timestamp)
169169
{
170170
uint32_t calc_time, blocks, offset;
171-
uint64_t aa;
171+
uint64_t aa;
172172

173173
calc_time = get_current_time();
174174
offset = timestamp - calc_time; // offset in useconds
175175

176176
if (offset > 0xf0000000u) // if offset is a really big number, assume that timer has already expired (i.e. negative)
177-
offset = 0u;
177+
offset = 0u;
178178

179179
if (offset > 10u) { // it takes 10us to user timer routine after interrupt. Offset timer to account for that.
180-
offset -= 10u;
180+
offset -= 10u;
181181
} else
182-
offset = 0u;
182+
offset = 0u;
183183

184184
aa = (uint64_t) offset;
185185
aa *= 26u; // convert from 1MHz to 26MHz clock. todo scale for other clock freqs
186186

187187
blocks = aa >> 7;
188188
blocks++; // round
189189

190-
largecnt = blocks>>1; // communicate to event_timer() routine
190+
largecnt = blocks>>1; // communicate to event_timer() routine
191191
}
192192

193193
static void event_timer()
194194
{
195195
if (largecnt) {
196-
uint32_t cnt = largecnt;
196+
uint32_t cnt = largecnt;
197197

198-
if (cnt > 65535u) {
199-
cnt = 0u;
200-
} else
201-
cnt = 65536u - cnt;
198+
if (cnt > 65535u) {
199+
cnt = 0u;
200+
} else {
201+
cnt = 65536u - cnt;
202+
}
202203

203-
tmr2Config.nLoad = cnt;
204-
tmr2Config.nAsyncLoad = cnt;
205-
adi_tmr_ConfigTimer(ADI_TMR_DEVICE_GP2, &tmr2Config);
204+
tmr2Config.nLoad = cnt;
205+
tmr2Config.nAsyncLoad = cnt;
206+
adi_tmr_ConfigTimer(ADI_TMR_DEVICE_GP2, &tmr2Config);
206207
adi_tmr_Enable(ADI_TMR_DEVICE_GP2, true);
207208
} else {
208-
us_ticker_irq_handler();
209+
us_ticker_irq_handler();
209210
}
210211
}
211212

@@ -222,16 +223,16 @@ static void event_timer()
222223
*/
223224
static void GP2CallbackFunction(void *pCBParam, uint32_t Event, void * pArg)
224225
{
225-
if (largecnt >= 65536u) {
226-
largecnt -= 65536u;
227-
} else {
228-
largecnt = 0;
226+
if (largecnt >= 65536u) {
227+
largecnt -= 65536u;
228+
} else {
229+
largecnt = 0;
229230
}
230231

231-
if (largecnt < 65536u) {
232-
adi_tmr_Enable(ADI_TMR_DEVICE_GP2, false);
233-
event_timer();
234-
}
232+
if (largecnt < 65536u) {
233+
adi_tmr_Enable(ADI_TMR_DEVICE_GP2, false);
234+
event_timer();
235+
}
235236
}
236237

237238

@@ -326,8 +327,8 @@ void us_ticker_set_interrupt(timestamp_t timestamp)
326327
* This MUST not be called if another timer event is currently enabled.
327328
*
328329
*/
329-
calc_event_counts(timestamp); // use timestamp to calculate largecnt to control number of timer interrupts
330-
event_timer(); // uses largecnt to initiate timer interrupts
330+
calc_event_counts(timestamp); // use timestamp to calculate largecnt to control number of timer interrupts
331+
event_timer(); // uses largecnt to initiate timer interrupts
331332
}
332333

333334
/** Set pending interrupt that should be fired right away.

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