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Merge pull request #4226 from Wiznet/master
[WIZnet][W7500*] Support for mbed OS 5
2 parents 7385a88 + 34da12a commit 444ff09

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‎targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/device/TOOLCHAIN_GCC_ARM/startup_W7500.S

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@@ -188,8 +188,8 @@ Reset_Handler:
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.LC3:
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#endif /* __STARTUP_CLEAR_BSS */
190190

191-
/*bl _start*/
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bl main
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bl _start
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//bl main
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.pool
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.size Reset_Handler, . - Reset_Handler

‎targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/device/TOOLCHAIN_IAR/W7500_Flash.icf

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/*###ICF### Section handled by ICF editor, don't touch! ****/
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/*-Editor annotation file-*/
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/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
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/*-Specials-*/
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define symbol __ICFEDIT_intvec_start__ = 0x00000000;
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/*-Memory Regions-*/
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define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
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define symbol __ICFEDIT_region_ROM_end__ = 0x00020000;
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define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
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define symbol __ICFEDIT_region_RAM_end__ = 0x20004000;
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/*-Sizes-*/
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define symbol __ICFEDIT_size_cstack__ = 0x00000400;
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define symbol __ICFEDIT_size_heap__ = 0x00000400;
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/**** End of ICF editor section. ###ICF###*/
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define memory mem with size = 4G;
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define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
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define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
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define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
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define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
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initialize by copy { readwrite };
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do not initialize { section .noinit };
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place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
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place in ROM_region { readonly };
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place in RAM_region { readwrite,
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block CSTACK, block HEAP };

‎targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/device/TOOLCHAIN_IAR/startup_W7500.s

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;/*******************************************************************************************************************************************************
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; * Copyright ¨Ï 2016 <WIZnet Co.,Ltd.>
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; * Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the ¡°Software¡±),
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; * to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense,
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; * and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions:
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; *
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; * The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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;
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; * THE SOFTWARE IS PROVIDED ¡°AS IS¡±, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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; * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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; * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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; * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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;*********************************************************************************************************************************************************/
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;/**************************************************************************//**
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; * @file startup_ARMCM0.s
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; * @brief CMSIS Core Device Startup File for
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; * ARMCM0 Device Series
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; * @version V1.08
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; * @date 23. November 2012
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; *
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; * @note
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; *
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; ******************************************************************************/
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;/* Copyright (c) 2011 - 2012 ARM LIMITED
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;
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; All rights reserved.
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; Redistribution and use in source and binary forms, with or without
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; modification, are permitted provided that the following conditions are met:
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; - Redistributions of source code must retain the above copyright
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; notice, this list of conditions and the following disclaimer.
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; - Redistributions in binary form must reproduce the above copyright
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; notice, this list of conditions and the following disclaimer in the
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; documentation and/or other materials provided with the distribution.
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; - Neither the name of ARM nor the names of its contributors may be used
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; to endorse or promote products derived from this software without
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; specific prior written permission.
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; *
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; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
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; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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; POSSIBILITY OF SUCH DAMAGE.
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; ---------------------------------------------------------------------------*/
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;
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; The modules in this file are included in the libraries, and may be replaced
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; by any user-defined modules that define the PUBLIC symbol _program_start or
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; a user defined start symbol.
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; To override the cstartup defined in the library, simply add your modified
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; version to the workbench project.
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;
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; The vector table is normally located at address 0.
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; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
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; The name "__vector_table" has special meaning for C-SPY:
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; it is where the SP start value is found, and the NVIC vector
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; table register (VTOR) is initialized to this address if != 0.
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;
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; Cortex-M version
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;
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MODULE ?cstartup
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;; Forward declaration of sections.
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SECTION CSTACK:DATA:NOROOT(3)
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SECTION .intvec:CODE:NOROOT(2)
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EXTERN __iar_program_start
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EXTERN SystemInit
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PUBLIC __vector_table
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PUBLIC __vector_table_0x1c
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PUBLIC __Vectors
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PUBLIC __Vectors_End
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PUBLIC __Vectors_Size
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DATA
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__vector_table
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DCD sfe(CSTACK)
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DCD Reset_Handler ; Reset Handler
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DCD NMI_Handler ; NMI Handler
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DCD HardFault_Handler ; Hard Fault Handler
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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__vector_table_0x1c
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD SVC_Handler ; SVCall Handler
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD PendSV_Handler ; PendSV Handler
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DCD SysTick_Handler ; SysTick Handler
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; Exterval Interrupts
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DCD SSP0_Handler ; 16+ 0: SSP 0 Handler
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DCD SSP1_Handler ; 16+ 1: SSP 1 Handler
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DCD UART0_Handler ; 16+ 2: UART 0 Handler
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DCD UART1_Handler ; 16+ 3: UART 1 Handler
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DCD UART2_Handler ; 16+ 4: UART 2 Handler
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DCD I2C0_Handler ; 16+ 5: I2C 0 Handler
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DCD I2C1_Handler ; 16+ 6: I2C 1 Handler
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DCD PORT0_Handler ; 16+ 7: GPIO Port 0 Combined Handler
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DCD PORT1_Handler ; 16+ 8: GPIO Port 1 Combined Handler
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DCD PORT2_Handler ; 16+ 9: GPIO Port 2 Combined Handler
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DCD PORT3_Handler ; 16+10: GPIO Port 3 Combined Handler
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DCD DMA_Handler ; 16+11: DMA Combined Handler
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DCD DUALTIMER0_Handler ; 16+12: Dual timer 0 handler
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DCD DUALTIMER1_Handler ; 16+13: Dual timer 1 handler
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DCD PWM0_Handler ; 16+14: PWM0 Handler
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DCD PWM1_Handler ; 16+15: PWM1 Handler
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DCD PWM2_Handler ; 16+16: PWM2 Handler
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DCD PWM3_Handler ; 16+17: PWM3 Handler
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DCD PWM4_Handler ; 16+18: PWM4 Handler
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DCD PWM5_Handler ; 16+19: PWM5 Handler
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DCD PWM6_Handler ; 16+20: PWM6 Handler
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DCD PWM7_Handler ; 16+21: PWM7 Handler
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DCD RTC_Handler ; 16+22: RTC Handler
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DCD ADC_Handler ; 16+23: ADC Handler
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DCD WZTOE_Handler ; 16+24: WZTOE_Handler
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DCD EXTI_Handler ; 16+25: EXTI_Handler
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__Vectors_End
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__Vectors EQU __vector_table
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__Vectors_Size EQU __Vectors_End - __Vectors
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;
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;; Default interrupt handlers.
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;;
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THUMB
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PUBWEAK Reset_Handler
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SECTION .text:CODE:REORDER:NOROOT(2)
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Reset_Handler
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LDR R0, =SystemInit
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BLX R0
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LDR R0, =__iar_program_start
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BX R0
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PUBWEAK NMI_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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NMI_Handler
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B NMI_Handler
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PUBWEAK HardFault_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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HardFault_Handler
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B HardFault_Handler
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PUBWEAK SVC_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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SVC_Handler
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B SVC_Handler
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PUBWEAK PendSV_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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PendSV_Handler
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B PendSV_Handler
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PUBWEAK SysTick_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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SysTick_Handler
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B SysTick_Handler
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PUBWEAK SSP0_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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SSP0_Handler
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B SSP0_Handler
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PUBWEAK SSP1_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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SSP1_Handler
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B SSP1_Handler
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PUBWEAK UART0_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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UART0_Handler
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B UART0_Handler
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PUBWEAK UART1_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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UART1_Handler
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B UART1_Handler
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PUBWEAK UART2_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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UART2_Handler
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B UART2_Handler
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PUBWEAK I2C0_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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I2C0_Handler
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B I2C0_Handler
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PUBWEAK I2C1_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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I2C1_Handler
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B I2C1_Handler
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PUBWEAK PORT0_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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PORT0_Handler
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B PORT0_Handler
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PUBWEAK PORT1_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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PORT1_Handler
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B PORT1_Handler
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PUBWEAK PORT2_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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PORT2_Handler
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B PORT2_Handler
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PUBWEAK PORT3_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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PORT3_Handler
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B PORT3_Handler
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PUBWEAK DMA_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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DMA_Handler
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B DMA_Handler
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PUBWEAK DUALTIMER0_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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DUALTIMER0_Handler
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B DUALTIMER0_Handler
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PUBWEAK DUALTIMER1_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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DUALTIMER1_Handler
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B DUALTIMER1_Handler
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PUBWEAK PWM0_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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PWM0_Handler
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B PWM0_Handler
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PUBWEAK PWM1_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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PWM1_Handler
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B PWM1_Handler
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PUBWEAK PWM2_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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PWM2_Handler
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B PWM2_Handler
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PUBWEAK PWM3_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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PWM3_Handler
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B PWM3_Handler
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PUBWEAK PWM4_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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PWM4_Handler
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B PWM4_Handler
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PUBWEAK PWM5_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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PWM5_Handler
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B PWM5_Handler
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PUBWEAK PWM6_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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PWM6_Handler
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B PWM6_Handler
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PUBWEAK PWM7_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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PWM7_Handler
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B PWM7_Handler
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PUBWEAK RTC_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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RTC_Handler
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B RTC_Handler
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PUBWEAK ADC_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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ADC_Handler
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B ADC_Handler
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PUBWEAK WZTOE_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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WZTOE_Handler
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B WZTOE_Handler
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PUBWEAK EXTI_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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EXTI_Handler
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B EXTI_Handler
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END

‎targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/device/TOOLCHAIN_GCC_ARM/startup_W7500.S

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -188,8 +188,8 @@ Reset_Handler:
188188
.LC3:
189189
#endif /* __STARTUP_CLEAR_BSS */
190190

191-
/*bl _start*/
192-
bl main
191+
bl _start
192+
//bl main
193193

194194
.pool
195195
.size Reset_Handler, . - Reset_Handler

‎targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/device/TOOLCHAIN_GCC_ARM/startup_W7500.o

-3.45 KB
Binary file not shown.

‎targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/device/TOOLCHAIN_IAR/W7500_Flash.icf

Lines changed: 31 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,31 @@
1+
/*###ICF### Section handled by ICF editor, don't touch! ****/
2+
/*-Editor annotation file-*/
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/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
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/*-Specials-*/
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define symbol __ICFEDIT_intvec_start__ = 0x00000000;
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/*-Memory Regions-*/
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define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
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define symbol __ICFEDIT_region_ROM_end__ = 0x00020000;
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define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
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define symbol __ICFEDIT_region_RAM_end__ = 0x20004000;
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/*-Sizes-*/
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define symbol __ICFEDIT_size_cstack__ = 0x00000400;
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define symbol __ICFEDIT_size_heap__ = 0x00000400;
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/**** End of ICF editor section. ###ICF###*/
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define memory mem with size = 4G;
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define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
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define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
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define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
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define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
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initialize by copy { readwrite };
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do not initialize { section .noinit };
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place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
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place in ROM_region { readonly };
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place in RAM_region { readwrite,
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block CSTACK, block HEAP };

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