Cortex M33: set DOMAIN_NS to 0 when TZ is not used

Author: jeromecoutant

tools/toolchains/arm.py

@@ -522,7 +522,7 @@ def __init__(self, target, *args, **kwargs):
                 self.flags['asm'].append("--library_type=microlib")
 
         core = target.core
-        if CORE_ARCH[target.core] == 8:
+        if CORE_ARCH[target.core] == 8 and "TFM" in target.labels:
             if ((not target.core.endswith("-NS")) and
                     kwargs.get('build_dir', False)):
                 # Create Secure library

tools/toolchains/gcc.py

@@ -61,7 +61,7 @@ def __init__(self, target,  notify=None, macros=None, build_profile=None,
 
         core = target.core
         self.cpu = []
-        if CORE_ARCH[target.core] == 8:
+        if CORE_ARCH[target.core] == 8 and "TFM" in target.labels:
             # Add linking time preprocessor macro DOMAIN_NS
             if target.core.endswith("-NS"):
                 self.flags["ld"].append("-DDOMAIN_NS=1")

tools/toolchains/iar.py

@@ -55,7 +55,7 @@ def __init__(self, target, notify=None, macros=None, build_profile=None,
             build_profile=build_profile
         )
         core = target.core
-        if CORE_ARCH[target.core] == 8:
+        if CORE_ARCH[target.core] == 8 and "TFM" in target.labels:
             # Add linking time preprocessor macro DOMAIN_NS
             if target.core.endswith("-NS"):
                 define_string = self.make_ld_define("DOMAIN_NS", "0x1")

tools/toolchains/mbed_toolchain.py

@@ -88,22 +88,22 @@
                         "__CMSIS_RTOS", "__EVAL", "__MBED_CMSIS_RTOS_CA9"],
     "Cortex-M23-NS":   ["__CORTEX_M23", "ARM_MATH_ARMV8MBL", "DOMAIN_NS=1",
                         "__CMSIS_RTOS", "__MBED_CMSIS_RTOS_CM"],
-    "Cortex-M23":      ["__CORTEX_M23", "ARM_MATH_ARMV8MBL", "__CMSIS_RTOS",
-                        "__MBED_CMSIS_RTOS_CM"],
+    "Cortex-M23":      ["__CORTEX_M23", "ARM_MATH_ARMV8MBL", "DOMAIN_NS=0",
+                        "__CMSIS_RTOS", "__MBED_CMSIS_RTOS_CM"],
     "Cortex-M33-NS":   ["__CORTEX_M33", "ARM_MATH_ARMV8MML", "DOMAIN_NS=1",
                         "__CMSIS_RTOS", "__MBED_CMSIS_RTOS_CM"],
-    "Cortex-M33":      ["__CORTEX_M33", "ARM_MATH_ARMV8MML", "__CMSIS_RTOS",
-                        "__MBED_CMSIS_RTOS_CM"],
+    "Cortex-M33":      ["__CORTEX_M33", "ARM_MATH_ARMV8MML", "DOMAIN_NS=0",
+                        "__CMSIS_RTOS", "__MBED_CMSIS_RTOS_CM"],
     "Cortex-M33F-NS":  ["__CORTEX_M33", "ARM_MATH_ARMV8MML", "DOMAIN_NS=1",
                         "__FPU_PRESENT=1U", "__CMSIS_RTOS",
                         "__MBED_CMSIS_RTOS_CM"],
-    "Cortex-M33F":     ["__CORTEX_M33", "ARM_MATH_ARMV8MML",
+    "Cortex-M33F":     ["__CORTEX_M33", "ARM_MATH_ARMV8MML", "DOMAIN_NS=0",
                         "__FPU_PRESENT=1U", "__CMSIS_RTOS",
                         "__MBED_CMSIS_RTOS_CM"],
     "Cortex-M33FE-NS": ["__CORTEX_M33", "ARM_MATH_ARMV8MML", "DOMAIN_NS=1",
                         "__FPU_PRESENT=1U", "__CMSIS_RTOS",
                         "__MBED_CMSIS_RTOS_CM", "__DSP_PRESENT=1U"],
-    "Cortex-M33FE":    ["__CORTEX_M33", "ARM_MATH_ARMV8MML",
+    "Cortex-M33FE":    ["__CORTEX_M33", "ARM_MATH_ARMV8MML", "DOMAIN_NS=0",
                         "__FPU_PRESENT=1U", "__CMSIS_RTOS",
                         "__MBED_CMSIS_RTOS_CM", "__DSP_PRESENT=1U"],
 }