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Merge pull request #11366 from 0xc0170/dev_rollup
Rollup part 2 for 5.14
2 parents 27571bc + de627da commit 4531229

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‎TESTS/mbed_hal/qspi/flash_configs/MX25LM51245G_config.h

Lines changed: 101 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,101 @@
1+
/* mbed Microcontroller Library
2+
* Copyright (c) 2018-2018 ARM Limited
3+
*
4+
* Licensed under the Apache License, Version 2.0 (the "License");
5+
* you may not use this file except in compliance with the License.
6+
* You may obtain a copy of the License at
7+
*
8+
* http://www.apache.org/licenses/LICENSE-2.0
9+
*
10+
* Unless required by applicable law or agreed to in writing, software
11+
* distributed under the License is distributed on an "AS IS" BASIS,
12+
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13+
* See the License for the specific language governing permissions and
14+
* limitations under the License.
15+
*/
16+
#ifndef MBED_QSPI_FLASH_MX25LM51245G_H
17+
#define MBED_QSPI_FLASH_MX25LM51245G_H
18+
19+
20+
#define QSPI_FLASH_CHIP_STRING "macronix MX25LM51245G"
21+
22+
// Command for reading status register
23+
#define QSPI_CMD_RDSR 0x05
24+
// Command for reading configuration register
25+
#define QSPI_CMD_RDCR0 0x15
26+
#define QSPI_CMD_RDCR1 0x71
27+
// Command for writing status/configuration register
28+
#define QSPI_CMD_WRSR 0x01
29+
// Command for reading security register
30+
#define QSPI_CMD_RDSCUR 0x2B
31+
32+
// Command for setting Reset Enable
33+
#define QSPI_CMD_RSTEN 0x66
34+
// Command for setting Reset
35+
#define QSPI_CMD_RST 0x99
36+
37+
// Command for setting write enable
38+
#define QSPI_CMD_WREN 0x06
39+
// Command for setting write disable
40+
#define QSPI_CMD_WRDI 0x04
41+
42+
// WRSR operations max time [us] (datasheet max time + 15%)
43+
#define QSPI_WRSR_MAX_TIME 34500 // 30ms
44+
// general wait max time [us]
45+
#define QSPI_WAIT_MAX_TIME 100000 // 100ms
46+
47+
48+
// Commands for writing (page programming)
49+
// Only single/octal mode supported with this memory
50+
// So only single 1-1-1 mode in this QSPI config
51+
#define QSPI_CMD_WRITE_1IO 0x02 // 1-1-1 mode
52+
// write operations max time [us] (datasheet max time + 15%)
53+
#define QSPI_PAGE_PROG_MAX_TIME 11500 // 10ms
54+
55+
#define QSPI_PAGE_SIZE 256 // 256B
56+
#define QSPI_SECTOR_SIZE 4096 // 4kB
57+
#define QSPI_SECTOR_COUNT 2048
58+
59+
// Commands for reading
60+
// Only single/octal mode supported with this memory
61+
// So only single 1-1-1 mode in this QSPI config
62+
#define QSPI_CMD_READ_1IO_FAST 0x0B // 1-1-1 mode
63+
#define QSPI_CMD_READ_1IO 0x03 // 1-1-1 mode
64+
65+
#define QSPI_READ_1IO_DUMMY_CYCLE 0
66+
#define QSPI_READ_FAST_DUMMY_CYCLE 8
67+
68+
// Commands for erasing
69+
#define QSPI_CMD_ERASE_SECTOR 0x20 // 4kB
70+
//#define QSPI_CMD_ERASE_BLOCK_32 // not supported, only ersae block 64
71+
#define QSPI_CMD_ERASE_BLOCK_64 0xD8 // 64kB
72+
#define QSPI_CMD_ERASE_CHIP 0x60 // or 0xC7
73+
74+
// erase operations max time [us] (datasheet max time + 15%)
75+
#define QSPI_ERASE_SECTOR_MAX_TIME 480000 // 400 ms
76+
#define QSPI_ERASE_BLOCK_64_MAX_TIME 2400000 // 2s
77+
78+
// max frequency for basic rw operation (for fast mode)
79+
#define QSPI_COMMON_MAX_FREQUENCY 1000000
80+
81+
#define QSPI_STATUS_REG_SIZE 1 //2 ??
82+
#define QSPI_CONFIG_REG_0_SIZE 1
83+
#define QSPI_CONFIG_REG_1_SIZE 1
84+
#define QSPI_SECURITY_REG_SIZE 1
85+
#define QSPI_MAX_REG_SIZE 2
86+
87+
// status register
88+
#define STATUS_BIT_WIP (1 << 0) // write in progress bit
89+
#define STATUS_BIT_WEL (1 << 1) // write enable latch
90+
#define STATUS_BIT_BP0 (1 << 2) //
91+
#define STATUS_BIT_BP1 (1 << 3) //
92+
#define STATUS_BIT_BP2 (1 << 4) //
93+
#define STATUS_BIT_BP3 (1 << 5) //
94+
//#define STATUS_BIT_QE (1 << 6) // Not supported
95+
//#define STATUS_BIT_SRWD (1 << 7) // Not supported
96+
97+
// configuration register 0
98+
// bit 0, 1, 2, 4, 5, 7 reserved
99+
#define CONFIG0_BIT_TB (1 << 3) // Top/Bottom area protect
100+
101+
#endif // MBED_QSPI_FLASH_MX25LM51245G_H

‎TESTS/mbed_hal/qspi/flash_configs/flash_configs.h

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -32,6 +32,9 @@
3232
#elif defined(TARGET_DISCO_F769NI)
3333
#include "MX25L51245G_config.h" // MX25L51245G
3434

35+
#elif defined(TARGET_DISCO_L4R9I)
36+
#include "MX25LM51245G_config.h" // MX25LM51245G
37+
3538
#elif defined(TARGET_DISCO_L476VG)
3639
#include "N25Q128A_config.h" // N25Q128A13EF840E
3740
/* See STM32L476 Errata Sheet, it is not possible to use Dual-/Quad-mode for the command phase */

‎TESTS/mbed_hal/qspi/main.cpp

Lines changed: 18 additions & 0 deletions
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‎TESTS/mbed_hal/qspi/qspi_test_utils.h

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -77,10 +77,19 @@ struct Qspi {
7777

7878

7979
#define READ_1_1_1 MODE_1_1_1, QSPI_CMD_READ_1IO, QSPI_READ_1IO_DUMMY_CYCLE
80+
#ifdef QSPI_CMD_READ_1I2O
8081
#define READ_1_1_2 MODE_1_1_2, QSPI_CMD_READ_1I2O, QSPI_READ_1I2O_DUMMY_CYCLE
82+
#endif
83+
#ifdef QSPI_CMD_READ_2IO
8184
#define READ_1_2_2 MODE_1_2_2, QSPI_CMD_READ_2IO, QSPI_READ_2IO_DUMMY_CYCLE
85+
#endif
86+
#ifdef QSPI_CMD_READ_1I4O
8287
#define READ_1_1_4 MODE_1_1_4, QSPI_CMD_READ_1I4O, QSPI_READ_1I4O_DUMMY_CYCLE
88+
#endif
89+
#ifdef QSPI_CMD_READ_4IO
8390
#define READ_1_4_4 MODE_1_4_4, QSPI_CMD_READ_4IO, QSPI_READ_4IO_DUMMY_CYCLE
91+
#endif
92+
8493
#ifdef QSPI_CMD_READ_DPI
8594
#define READ_2_2_2 MODE_2_2_2, QSPI_CMD_READ_DPI, QSPI_READ_2IO_DUMMY_CYCLE
8695
#endif

‎features/cellular/framework/AT/ATHandler.cpp

Lines changed: 13 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -722,7 +722,19 @@ int32_t ATHandler::read_int()
722722
return -1;
723723
}
724724

725-
return std::strtol(buff, NULL, 10);
725+
errno = 0;
726+
char *endptr;
727+
long result = std::strtol(buff, &endptr, 10);
728+
if ((result == LONG_MIN || result == LONG_MAX) && errno == ERANGE) {
729+
return -1; // overflow/underflow
730+
}
731+
if (result < 0) {
732+
return -1; // negative values are unsupported
733+
}
734+
if (*buff == '\0') {
735+
return -1; // empty string
736+
}
737+
return (int32_t) result;
726738
}
727739

728740
void ATHandler::set_delimiter(char delimiter)

‎features/cellular/framework/AT/ATHandler.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -416,9 +416,9 @@ class ATHandler {
416416
*/
417417
ssize_t read_hex_string(char *str, size_t size);
418418

419-
/** Reads as string and converts result to integer. Supports only positive integers.
419+
/** Reads as string and converts result to integer. Supports only non-negative integers.
420420
*
421-
* @return the positive integer or -1 in case of error.
421+
* @return the non-negative integer or -1 in case of error.
422422
*/
423423
int32_t read_int();
424424

‎features/storage/kvstore/tdbstore/TDBStore.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1414,7 +1414,7 @@ int TDBStore::do_reserved_data_get(void *reserved_data, size_t reserved_data_buf
14141414

14151415
while (actual_size) {
14161416
uint32_t chunk = std::min(work_buf_size, (uint32_t) actual_size);
1417-
ret = read_area(_active_area, offset, chunk, buf);
1417+
ret = read_area(_active_area, offset, chunk, buf + offset);
14181418
if (ret) {
14191419
return ret;
14201420
}

‎rtos/source/Mutex.cpp

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -97,6 +97,7 @@ bool Mutex::trylock_for(uint32_t millisec)
9797
{
9898
osStatus status = osMutexAcquire(_id, millisec);
9999
if (status == osOK) {
100+
_count++;
100101
return true;
101102
}
102103

‎targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_i2c.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2592,7 +2592,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c,
25922592
/* Prepare transfer parameters */
25932593
hi2c->pBuffPtr = pData;
25942594
hi2c->XferCount = Size;
2595-
hi2c->XferOptions = (XferOptions & (~I2C_RELOAD_MODE));
2595+
hi2c->XferOptions = XferOptions;
25962596
hi2c->XferISR = I2C_Master_ISR_IT;
25972597

25982598
/* If size > MAX_NBYTE_SIZE, use reload mode */
@@ -2658,7 +2658,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c,
26582658
/* Prepare transfer parameters */
26592659
hi2c->pBuffPtr = pData;
26602660
hi2c->XferCount = Size;
2661-
hi2c->XferOptions = (XferOptions & (~I2C_RELOAD_MODE));
2661+
hi2c->XferOptions = XferOptions;
26622662
hi2c->XferISR = I2C_Master_ISR_IT;
26632663

26642664
/* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */

‎targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_i2c.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2592,7 +2592,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c,
25922592
/* Prepare transfer parameters */
25932593
hi2c->pBuffPtr = pData;
25942594
hi2c->XferCount = Size;
2595-
hi2c->XferOptions = (XferOptions & (~I2C_RELOAD_MODE)); // MBED patch
2595+
hi2c->XferOptions = XferOptions;
25962596
hi2c->XferISR = I2C_Master_ISR_IT;
25972597

25982598
/* If size > MAX_NBYTE_SIZE, use reload mode */
@@ -2666,7 +2666,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c,
26662666
/* Prepare transfer parameters */
26672667
hi2c->pBuffPtr = pData;
26682668
hi2c->XferCount = Size;
2669-
hi2c->XferOptions = (XferOptions & (~I2C_RELOAD_MODE)); // MBED patch
2669+
hi2c->XferOptions = XferOptions;
26702670
hi2c->XferISR = I2C_Master_ISR_IT;
26712671

26722672
/* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */

‎targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/objects.h

Lines changed: 0 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -44,16 +44,6 @@ struct trng_s {
4444
RNG_HandleTypeDef handle;
4545
};
4646

47-
struct qspi_s {
48-
QSPI_HandleTypeDef handle;
49-
PinName io0;
50-
PinName io1;
51-
PinName io2;
52-
PinName io3;
53-
PinName sclk;
54-
PinName ssel;
55-
};
56-
5747
#include "common_objects.h"
5848

5949
#ifdef __cplusplus

‎targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/TARGET_SDP_K1/PinNames.h

Lines changed: 16 additions & 27 deletions
Original file line numberDiff line numberDiff line change
@@ -284,12 +284,12 @@ typedef enum {
284284
D7 = PG_10,
285285
D8 = PG_11,
286286
D9 = PB_15,
287-
D10 = PA_15,
288-
D11 = PA_7,
289-
D12 = PB_4,
290-
D13 = PB_3,
291-
D14 = PB_7,
292-
D15 = PB_8,
287+
D10 = PA_15, // SPI CS
288+
D11 = PA_7, // SPI MOSI
289+
D12 = PB_4, // SPI MISO
290+
D13 = PB_3, // SPI SCK
291+
D14 = PB_7, // I2C SDA
292+
D15 = PB_8, // I2C SCL
293293

294294
// STDIO for console print
295295
#ifdef MBED_CONF_TARGET_STDIO_UART_TX
@@ -310,43 +310,35 @@ typedef enum {
310310
LED2 = PK_6, // Orange LED
311311
LED3 = PK_5, // Green LED
312312
LED4 = PK_4,
313-
LED_RED = LED1,
314-
LED_ORANGE = LED2,
315-
LED_GREEN = LED3,
316313
SERIAL_TX = STDIO_UART_TX,
317314
SERIAL_RX = STDIO_UART_RX,
318315
USBTX = STDIO_UART_TX,
319316
USBRX = STDIO_UART_RX,
320-
321317

322318
// Adding these signals for the SDP connector
323-
SDP_SPI_MOSI = PF_9, // SDP Connector for SPI lines
324-
SDP_SPI_MISO = PF_8,
319+
SDP_SPI_MOSI = PF_9, // SDP Connector for SPI lines
320+
SDP_SPI_MISO = PF_8,
325321
SDP_SPI_SCK = PH_6,
326322
SDP_SPI_CS_A = PB_9,
327323
SDP_SPI_CS_B = PC_6,
328324
SDP_SPI_CS_C = PC_7,
329-
SDP_I2C_SDA = PC_9, // SDP Connector I2C lines
325+
SDP_I2C_SDA = PC_9, // SDP Connector I2C lines
330326
SDP_I2C_SCL = PH_7,
331-
SDP_GPIO_0 = PJ_0, // SDP connector GPIO 0-7
327+
SDP_GPIO_0 = PJ_0, // SDP connector GPIO 0-7
332328
SDP_GPIO_1 = PJ_1,
333329
SDP_GPIO_2 = PJ_3,
334330
SDP_GPIO_3 = PJ_4,
335331
SDP_GPIO_4 = PJ_5,
336332
SDP_GPIO_5 = PJ_12,
337333
SDP_GPIO_6 = PJ_13,
338-
SDP_GPIO_7 = PJ_14,
339-
SDP_UART_TX = PD_5, // SDP connector UART
334+
SDP_GPIO_7 = PJ_14,
335+
SDP_UART_TX = PD_5, // SDP connector UART
340336
SDP_UART_RX = PD_6,
341-
SDP_TMR_A = PB_14, // SDP connector TMR A, B & D
337+
SDP_TMR_A = PB_14, // SDP connector TMR A, B & D
342338
SDP_TMR_B = PE_6,
343339
SDP_TMR_D = PC_8,
344340

345-
/**** USB pins ****/
346-
USB_OTG_HS_DM = PB_14,
347-
USB_OTG_HS_DP = PB_15,
348-
USB_OTG_HS_ID = PB_12,
349-
USB_OTG_HS_SOF = PA_4,
341+
/**** USB pins ****/
350342
USB_OTG_HS_ULPI_CK = PA_5,
351343
USB_OTG_HS_ULPI_D0 = PA_3,
352344
USB_OTG_HS_ULPI_D1 = PB_0,
@@ -356,12 +348,9 @@ typedef enum {
356348
USB_OTG_HS_ULPI_D5 = PB_12,
357349
USB_OTG_HS_ULPI_D6 = PB_13,
358350
USB_OTG_HS_ULPI_D7 = PB_5,
359-
USB_OTG_HS_ULPI_DIR = PI_11,
360-
USB_OTG_HS_ULPI_DIR_ALT0 = PC_2,
361-
USB_OTG_HS_ULPI_NXT = PH_4,
362-
USB_OTG_HS_ULPI_NXT_ALT0 = PC_3,
351+
USB_OTG_HS_ULPI_DIR = PC_2,
352+
USB_OTG_HS_ULPI_NXT = PC_3,
363353
USB_OTG_HS_ULPI_STP = PC_0,
364-
USB_OTG_HS_VBUS = PB_13,
365354

366355
/**** OSCILLATOR pins ****/
367356
RCC_OSC32_IN = PC_14,

‎targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/objects.h

Lines changed: 0 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -58,16 +58,6 @@ struct trng_s {
5858
RNG_HandleTypeDef handle;
5959
};
6060

61-
struct qspi_s {
62-
QSPI_HandleTypeDef handle;
63-
PinName io0;
64-
PinName io1;
65-
PinName io2;
66-
PinName io3;
67-
PinName sclk;
68-
PinName ssel;
69-
};
70-
7161
#include "common_objects.h"
7262

7363
#ifdef __cplusplus

‎targets/TARGET_STM/TARGET_STM32F4/common_objects.h

Lines changed: 17 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -143,6 +143,23 @@ struct can_s {
143143
};
144144
#endif
145145

146+
#if DEVICE_QSPI
147+
struct qspi_s {
148+
#if defined(OCTOSPI1)
149+
OSPI_HandleTypeDef handle;
150+
#else
151+
QSPI_HandleTypeDef handle;
152+
#endif
153+
QSPIName qspi;
154+
PinName io0;
155+
PinName io1;
156+
PinName io2;
157+
PinName io3;
158+
PinName sclk;
159+
PinName ssel;
160+
};
161+
#endif
162+
146163
#ifdef __cplusplus
147164
}
148165
#endif

‎targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/objects.h

Lines changed: 0 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -58,16 +58,6 @@ struct trng_s {
5858
RNG_HandleTypeDef handle;
5959
};
6060

61-
struct qspi_s {
62-
QSPI_HandleTypeDef handle;
63-
PinName io0;
64-
PinName io1;
65-
PinName io2;
66-
PinName io3;
67-
PinName sclk;
68-
PinName ssel;
69-
};
70-
7161
#include "common_objects.h"
7262

7363
#ifdef __cplusplus

‎targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/objects.h

Lines changed: 0 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -58,16 +58,6 @@ struct trng_s {
5858
RNG_HandleTypeDef handle;
5959
};
6060

61-
struct qspi_s {
62-
QSPI_HandleTypeDef handle;
63-
PinName io0;
64-
PinName io1;
65-
PinName io2;
66-
PinName io3;
67-
PinName sclk;
68-
PinName ssel;
69-
};
70-
7161
#include "common_objects.h"
7262

7363
#ifdef __cplusplus

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