F1 CUBE V1.5.0

HAL V1.1.0
LL V1.1.0
CMSIS V4.2.0

Author: LMESTM

targets/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/device/stm32f103xb.h

@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f1xx.h
   * @author  MCD Application Team
-  * @version V4.1.0
-  * @date    29-April-2016
+  * @version V4.2.0
+  * @date    31-March-2017
   * @brief   CMSIS STM32F1xx Device Peripheral Access Layer Header File. 
   *
   *          The file is the unique include file that the application programmer
@@ -18,7 +18,7 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -108,10 +108,10 @@
 #endif /* USE_HAL_DRIVER */
 
 /**
-  * @brief CMSIS Device version number V4.0.0
+  * @brief CMSIS Device version number V4.2.0
   */
-#define __STM32F1_CMSIS_VERSION_MAIN   (0x04) /*!< [31:24] main version */                                  
-#define __STM32F1_CMSIS_VERSION_SUB1   (0x01) /*!< [23:16] sub1 version */
+#define __STM32F1_CMSIS_VERSION_MAIN   (0x04) /*!< [31:24] main version */
+#define __STM32F1_CMSIS_VERSION_SUB1   (0x02) /*!< [23:16] sub1 version */
 #define __STM32F1_CMSIS_VERSION_SUB2   (0x00) /*!< [15:8]  sub2 version */
 #define __STM32F1_CMSIS_VERSION_RC     (0x00) /*!< [7:0]  release candidate */ 
 #define __STM32F1_CMSIS_VERSION        ((__STM32F1_CMSIS_VERSION_MAIN << 24)\

targets/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/device/stm32f1xx.h

@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    system_stm32f1xx.c
   * @author  MCD Application Team
-  * @version V4.1.0
-  * @date    29-April-2016
+  * @version V4.2.0
+  * @date    31-March-2017
   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
   * 
   * 1.  This file provides two functions and one global variable to be called from 
@@ -52,7 +52,7 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -111,12 +111,12 @@
   */
 
 #if !defined  (HSE_VALUE) 
-  #define HSE_VALUE    ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz.
+  #define HSE_VALUE               8000000U /*!< Default value of the External oscillator in Hz.
                                                 This value can be provided and adapted by the user application. */
 #endif /* HSE_VALUE */
 
 #if !defined  (HSI_VALUE)
-  #define HSI_VALUE    ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz.
+  #define HSI_VALUE               8000000U /*!< Default value of the Internal oscillator in Hz.
                                                 This value can be provided and adapted by the user application. */
 #endif /* HSI_VALUE */
 
@@ -128,7 +128,7 @@
 /*!< Uncomment the following line if you need to relocate your vector Table in
      Internal SRAM. */ 
 /* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
+#define VECT_TAB_OFFSET  0x00000000U /*!< Vector Table base offset field. 
                                   This value must be a multiple of 0x200. */
 
 
@@ -156,13 +156,13 @@
 *  Clock Definitions
 *******************************************************************************/
 #if defined(STM32F100xB) ||defined(STM32F100xE)
-  uint32_t SystemCoreClock         = 24000000;        /*!< System Clock Frequency (Core Clock) */
+  uint32_t SystemCoreClock         = 24000000U;        /*!< System Clock Frequency (Core Clock) */
 #else /*!< HSI Selected as System Clock source */
-  uint32_t SystemCoreClock         = 72000000;        /*!< System Clock Frequency (Core Clock) */
+  uint32_t SystemCoreClock         = 72000000U;        /*!< System Clock Frequency (Core Clock) */
 #endif
 
-const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-const uint8_t APBPrescTable[8] =  {0, 0, 0, 0, 1, 2, 3, 4};
+const uint8_t AHBPrescTable[16U] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+const uint8_t APBPrescTable[8U] =  {0, 0, 0, 0, 1, 2, 3, 4};
 
 /**
   * @}
@@ -204,42 +204,42 @@ void SystemInit (void)
 {
   /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
   /* Set HSION bit */
-  RCC->CR |= (uint32_t)0x00000001;
+  RCC->CR |= 0x00000001U;
 
   /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
 #if !defined(STM32F105xC) && !defined(STM32F107xC)
-  RCC->CFGR &= (uint32_t)0xF8FF0000;
+  RCC->CFGR &= 0xF8FF0000U;
 #else
-  RCC->CFGR &= (uint32_t)0xF0FF0000;
+  RCC->CFGR &= 0xF0FF0000U;
 #endif /* STM32F105xC */   
 
   /* Reset HSEON, CSSON and PLLON bits */
-  RCC->CR &= (uint32_t)0xFEF6FFFF;
+  RCC->CR &= 0xFEF6FFFFU;
 
   /* Reset HSEBYP bit */
-  RCC->CR &= (uint32_t)0xFFFBFFFF;
+  RCC->CR &= 0xFFFBFFFFU;
 
   /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
-  RCC->CFGR &= (uint32_t)0xFF80FFFF;
+  RCC->CFGR &= 0xFF80FFFFU;
 
 #if defined(STM32F105xC) || defined(STM32F107xC)
   /* Reset PLL2ON and PLL3ON bits */
-  RCC->CR &= (uint32_t)0xEBFFFFFF;
+  RCC->CR &= 0xEBFFFFFFU;
 
   /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x00FF0000;
+  RCC->CIR = 0x00FF0000U;
 
   /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;
+  RCC->CFGR2 = 0x00000000U;
 #elif defined(STM32F100xB) || defined(STM32F100xE)
   /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
+  RCC->CIR = 0x009F0000U;
 
   /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;      
+  RCC->CFGR2 = 0x00000000U;      
 #else
   /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
+  RCC->CIR = 0x009F0000U;
 #endif /* STM32F105xC */
 
 #if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
@@ -304,52 +304,52 @@ void SystemInit (void)
   */
 void SystemCoreClockUpdate (void)
 {
-  uint32_t tmp = 0, pllmull = 0, pllsource = 0;
+  uint32_t tmp = 0U, pllmull = 0U, pllsource = 0U;
 
 #if defined(STM32F105xC) || defined(STM32F107xC)
-  uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
+  uint32_t prediv1source = 0U, prediv1factor = 0U, prediv2factor = 0U, pll2mull = 0U;
 #endif /* STM32F105xC */
 
 #if defined(STM32F100xB) || defined(STM32F100xE)
-  uint32_t prediv1factor = 0;
+  uint32_t prediv1factor = 0U;
 #endif /* STM32F100xB or STM32F100xE */
 
   /* Get SYSCLK source -------------------------------------------------------*/
   tmp = RCC->CFGR & RCC_CFGR_SWS;
 
   switch (tmp)
   {
-    case 0x00:  /* HSI used as system clock */
+    case 0x00U:  /* HSI used as system clock */
       SystemCoreClock = HSI_VALUE;
       break;
-    case 0x04:  /* HSE used as system clock */
+    case 0x04U:  /* HSE used as system clock */
       SystemCoreClock = HSE_VALUE;
       break;
-    case 0x08:  /* PLL used as system clock */
+    case 0x08U:  /* PLL used as system clock */
 
       /* Get PLL clock source and multiplication factor ----------------------*/
       pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
 
 #if !defined(STM32F105xC) && !defined(STM32F107xC)      
-      pllmull = ( pllmull >> 18) + 2;
+      pllmull = ( pllmull >> 18U) + 2U;
 
-      if (pllsource == 0x00)
+      if (pllsource == 0x00U)
       {
         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
+        SystemCoreClock = (HSI_VALUE >> 1U) * pllmull;
       }
       else
       {
  #if defined(STM32F100xB) || defined(STM32F100xE)
-       prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
+       prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1U;
        /* HSE oscillator clock selected as PREDIV1 clock entry */
        SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
  #else
         /* HSE selected as PLL clock entry */
         if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
         {/* HSE oscillator clock divided by 2 */
-          SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
+          SystemCoreClock = (HSE_VALUE >> 1U) * pllmull;
         }
         else
         {
@@ -358,30 +358,30 @@ void SystemCoreClockUpdate (void)
  #endif
       }
 #else
-      pllmull = pllmull >> 18;
+      pllmull = pllmull >> 18U;
 
-      if (pllmull != 0x0D)
+      if (pllmull != 0x0DU)
       {
-         pllmull += 2;
+         pllmull += 2U;
       }
       else
       { /* PLL multiplication factor = PLL input clock * 6.5 */
-        pllmull = 13 / 2; 
+        pllmull = 13U / 2U; 
       }
 
-      if (pllsource == 0x00)
+      if (pllsource == 0x00U)
       {
         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
+        SystemCoreClock = (HSI_VALUE >> 1U) * pllmull;
       }
       else
       {/* PREDIV1 selected as PLL clock entry */
 
         /* Get PREDIV1 clock source and division factor */
         prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
-        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
+        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1U;
 
-        if (prediv1source == 0)
+        if (prediv1source == 0U)
         { 
           /* HSE oscillator clock selected as PREDIV1 clock entry */
           SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;          
@@ -390,8 +390,8 @@ void SystemCoreClockUpdate (void)
         {/* PLL2 clock selected as PREDIV1 clock entry */
 
           /* Get PREDIV2 division factor and PLL2 multiplication factor */
-          prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
-          pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; 
+          prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4U) + 1U;
+          pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8U) + 2U; 
           SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         
         }
       }
@@ -405,7 +405,7 @@ void SystemCoreClockUpdate (void)
 
   /* Compute HCLK clock frequency ----------------*/
   /* Get HCLK prescaler */
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4U)];
   /* HCLK clock frequency */
   SystemCoreClock >>= tmp;  
 }
@@ -434,13 +434,13 @@ void SystemInit_ExtMemCtl(void)
     required, then adjust the Register Addresses */
 
   /* Enable FSMC clock */
-  RCC->AHBENR = 0x00000114;
+  RCC->AHBENR = 0x00000114U;
 
   /* Delay after an RCC peripheral clock enabling */
   tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);
 
   /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
-  RCC->APB2ENR = 0x000001E0;
+  RCC->APB2ENR = 0x000001E0U;
 
   /* Delay after an RCC peripheral clock enabling */
   tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN);
@@ -453,23 +453,23 @@ void SystemInit_ExtMemCtl(void)
 /*----------------  NE3 configuration ----------------------------------------*/
 /*----------------  NBL0, NBL1 configuration ---------------------------------*/
 
-  GPIOD->CRL = 0x44BB44BB;  
-  GPIOD->CRH = 0xBBBBBBBB;
+  GPIOD->CRL = 0x44BB44BBU;  
+  GPIOD->CRH = 0xBBBBBBBBU;
 
-  GPIOE->CRL = 0xB44444BB;  
-  GPIOE->CRH = 0xBBBBBBBB;
+  GPIOE->CRL = 0xB44444BBU;  
+  GPIOE->CRH = 0xBBBBBBBBU;
 
-  GPIOF->CRL = 0x44BBBBBB;  
-  GPIOF->CRH = 0xBBBB4444;
+  GPIOF->CRL = 0x44BBBBBBU;  
+  GPIOF->CRH = 0xBBBB4444U;
 
-  GPIOG->CRL = 0x44BBBBBB;  
-  GPIOG->CRH = 0x444B4B44;
+  GPIOG->CRL = 0x44BBBBBBU;  
+  GPIOG->CRH = 0x444B4B44U;
 
 /*----------------  FSMC Configuration ---------------------------------------*/  
 /*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
 
-  FSMC_Bank1->BTCR[4] = 0x00001091;
-  FSMC_Bank1->BTCR[5] = 0x00110212;
+  FSMC_Bank1->BTCR[4U] = 0x00001091U;
+  FSMC_Bank1->BTCR[5U] = 0x00110212U;
 }
 #endif /* DATA_IN_ExtSRAM */
 #endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */

targets/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/device/system_stm32f1xx.c

@@ -2,13 +2,13 @@
   ******************************************************************************
   * @file    system_stm32f10x.h
   * @author  MCD Application Team
-  * @version V4.1.0
-  * @date    29-April-2016
+  * @version V4.2.0
+  * @date    31-March-2017
   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Header File.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -67,8 +67,8 @@
   */
 
 extern uint32_t SystemCoreClock;          /*!< System Clock Frequency (Core Clock) */
-extern const uint8_t  AHBPrescTable[16];  /*!< AHB prescalers table values */
-extern const uint8_t  APBPrescTable[8];   /*!< APB prescalers table values */
+extern const uint8_t  AHBPrescTable[16U];  /*!< AHB prescalers table values */
+extern const uint8_t  APBPrescTable[8U];   /*!< APB prescalers table values */
 
 /**
   * @}