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bulislawbulislaw
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Remove redefinitions of register macros from target code
1 parent 8fe62df commit 484d144

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-136
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4 files changed

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‎targets/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/device/stm32l152xc.h

Lines changed: 0 additions & 34 deletions
Original file line numberDiff line numberDiff line change
@@ -8631,58 +8631,24 @@ typedef struct
86318631

86328632
/******************* Bit definition for SCB_CFSR register *******************/
86338633
/*!< MFSR */
8634-
#define SCB_CFSR_IACCVIOL_Pos (0U)
8635-
#define SCB_CFSR_IACCVIOL_Msk (0x1U << SCB_CFSR_IACCVIOL_Pos) /*!< 0x00000001 */
86368634
#define SCB_CFSR_IACCVIOL SCB_CFSR_IACCVIOL_Msk /*!< Instruction access violation */
8637-
#define SCB_CFSR_DACCVIOL_Pos (1U)
8638-
#define SCB_CFSR_DACCVIOL_Msk (0x1U << SCB_CFSR_DACCVIOL_Pos) /*!< 0x00000002 */
86398635
#define SCB_CFSR_DACCVIOL SCB_CFSR_DACCVIOL_Msk /*!< Data access violation */
8640-
#define SCB_CFSR_MUNSTKERR_Pos (3U)
8641-
#define SCB_CFSR_MUNSTKERR_Msk (0x1U << SCB_CFSR_MUNSTKERR_Pos) /*!< 0x00000008 */
86428636
#define SCB_CFSR_MUNSTKERR SCB_CFSR_MUNSTKERR_Msk /*!< Unstacking error */
8643-
#define SCB_CFSR_MSTKERR_Pos (4U)
8644-
#define SCB_CFSR_MSTKERR_Msk (0x1U << SCB_CFSR_MSTKERR_Pos) /*!< 0x00000010 */
86458637
#define SCB_CFSR_MSTKERR SCB_CFSR_MSTKERR_Msk /*!< Stacking error */
8646-
#define SCB_CFSR_MMARVALID_Pos (7U)
8647-
#define SCB_CFSR_MMARVALID_Msk (0x1U << SCB_CFSR_MMARVALID_Pos) /*!< 0x00000080 */
86488638
#define SCB_CFSR_MMARVALID SCB_CFSR_MMARVALID_Msk /*!< Memory Manage Address Register address valid flag */
86498639
/*!< BFSR */
8650-
#define SCB_CFSR_IBUSERR_Pos (8U)
8651-
#define SCB_CFSR_IBUSERR_Msk (0x1U << SCB_CFSR_IBUSERR_Pos) /*!< 0x00000100 */
86528640
#define SCB_CFSR_IBUSERR SCB_CFSR_IBUSERR_Msk /*!< Instruction bus error flag */
8653-
#define SCB_CFSR_PRECISERR_Pos (9U)
8654-
#define SCB_CFSR_PRECISERR_Msk (0x1U << SCB_CFSR_PRECISERR_Pos) /*!< 0x00000200 */
86558641
#define SCB_CFSR_PRECISERR SCB_CFSR_PRECISERR_Msk /*!< Precise data bus error */
8656-
#define SCB_CFSR_IMPRECISERR_Pos (10U)
8657-
#define SCB_CFSR_IMPRECISERR_Msk (0x1U << SCB_CFSR_IMPRECISERR_Pos) /*!< 0x00000400 */
86588642
#define SCB_CFSR_IMPRECISERR SCB_CFSR_IMPRECISERR_Msk /*!< Imprecise data bus error */
8659-
#define SCB_CFSR_UNSTKERR_Pos (11U)
8660-
#define SCB_CFSR_UNSTKERR_Msk (0x1U << SCB_CFSR_UNSTKERR_Pos) /*!< 0x00000800 */
86618643
#define SCB_CFSR_UNSTKERR SCB_CFSR_UNSTKERR_Msk /*!< Unstacking error */
8662-
#define SCB_CFSR_STKERR_Pos (12U)
8663-
#define SCB_CFSR_STKERR_Msk (0x1U << SCB_CFSR_STKERR_Pos) /*!< 0x00001000 */
86648644
#define SCB_CFSR_STKERR SCB_CFSR_STKERR_Msk /*!< Stacking error */
8665-
#define SCB_CFSR_BFARVALID_Pos (15U)
8666-
#define SCB_CFSR_BFARVALID_Msk (0x1U << SCB_CFSR_BFARVALID_Pos) /*!< 0x00008000 */
86678645
#define SCB_CFSR_BFARVALID SCB_CFSR_BFARVALID_Msk /*!< Bus Fault Address Register address valid flag */
86688646
/*!< UFSR */
8669-
#define SCB_CFSR_UNDEFINSTR_Pos (16U)
8670-
#define SCB_CFSR_UNDEFINSTR_Msk (0x1U << SCB_CFSR_UNDEFINSTR_Pos) /*!< 0x00010000 */
86718647
#define SCB_CFSR_UNDEFINSTR SCB_CFSR_UNDEFINSTR_Msk /*!< The processor attempt to excecute an undefined instruction */
8672-
#define SCB_CFSR_INVSTATE_Pos (17U)
8673-
#define SCB_CFSR_INVSTATE_Msk (0x1U << SCB_CFSR_INVSTATE_Pos) /*!< 0x00020000 */
86748648
#define SCB_CFSR_INVSTATE SCB_CFSR_INVSTATE_Msk /*!< Invalid combination of EPSR and instruction */
8675-
#define SCB_CFSR_INVPC_Pos (18U)
8676-
#define SCB_CFSR_INVPC_Msk (0x1U << SCB_CFSR_INVPC_Pos) /*!< 0x00040000 */
86778649
#define SCB_CFSR_INVPC SCB_CFSR_INVPC_Msk /*!< Attempt to load EXC_RETURN into pc illegally */
8678-
#define SCB_CFSR_NOCP_Pos (19U)
8679-
#define SCB_CFSR_NOCP_Msk (0x1U << SCB_CFSR_NOCP_Pos) /*!< 0x00080000 */
86808650
#define SCB_CFSR_NOCP SCB_CFSR_NOCP_Msk /*!< Attempt to use a coprocessor instruction */
8681-
#define SCB_CFSR_UNALIGNED_Pos (24U)
8682-
#define SCB_CFSR_UNALIGNED_Msk (0x1U << SCB_CFSR_UNALIGNED_Pos) /*!< 0x01000000 */
86838651
#define SCB_CFSR_UNALIGNED SCB_CFSR_UNALIGNED_Msk /*!< Fault occurs when there is an attempt to make an unaligned memory access */
8684-
#define SCB_CFSR_DIVBYZERO_Pos (25U)
8685-
#define SCB_CFSR_DIVBYZERO_Msk (0x1U << SCB_CFSR_DIVBYZERO_Pos) /*!< 0x02000000 */
86868652
#define SCB_CFSR_DIVBYZERO SCB_CFSR_DIVBYZERO_Msk /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */
86878653

86888654
/******************* Bit definition for SCB_HFSR register *******************/

‎targets/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/device/stm32l152xe.h

Lines changed: 0 additions & 34 deletions
Original file line numberDiff line numberDiff line change
@@ -8933,58 +8933,24 @@ typedef struct
89338933

89348934
/******************* Bit definition for SCB_CFSR register *******************/
89358935
/*!< MFSR */
8936-
#define SCB_CFSR_IACCVIOL_Pos (0U)
8937-
#define SCB_CFSR_IACCVIOL_Msk (0x1U << SCB_CFSR_IACCVIOL_Pos) /*!< 0x00000001 */
89388936
#define SCB_CFSR_IACCVIOL SCB_CFSR_IACCVIOL_Msk /*!< Instruction access violation */
8939-
#define SCB_CFSR_DACCVIOL_Pos (1U)
8940-
#define SCB_CFSR_DACCVIOL_Msk (0x1U << SCB_CFSR_DACCVIOL_Pos) /*!< 0x00000002 */
89418937
#define SCB_CFSR_DACCVIOL SCB_CFSR_DACCVIOL_Msk /*!< Data access violation */
8942-
#define SCB_CFSR_MUNSTKERR_Pos (3U)
8943-
#define SCB_CFSR_MUNSTKERR_Msk (0x1U << SCB_CFSR_MUNSTKERR_Pos) /*!< 0x00000008 */
89448938
#define SCB_CFSR_MUNSTKERR SCB_CFSR_MUNSTKERR_Msk /*!< Unstacking error */
8945-
#define SCB_CFSR_MSTKERR_Pos (4U)
8946-
#define SCB_CFSR_MSTKERR_Msk (0x1U << SCB_CFSR_MSTKERR_Pos) /*!< 0x00000010 */
89478939
#define SCB_CFSR_MSTKERR SCB_CFSR_MSTKERR_Msk /*!< Stacking error */
8948-
#define SCB_CFSR_MMARVALID_Pos (7U)
8949-
#define SCB_CFSR_MMARVALID_Msk (0x1U << SCB_CFSR_MMARVALID_Pos) /*!< 0x00000080 */
89508940
#define SCB_CFSR_MMARVALID SCB_CFSR_MMARVALID_Msk /*!< Memory Manage Address Register address valid flag */
89518941
/*!< BFSR */
8952-
#define SCB_CFSR_IBUSERR_Pos (8U)
8953-
#define SCB_CFSR_IBUSERR_Msk (0x1U << SCB_CFSR_IBUSERR_Pos) /*!< 0x00000100 */
89548942
#define SCB_CFSR_IBUSERR SCB_CFSR_IBUSERR_Msk /*!< Instruction bus error flag */
8955-
#define SCB_CFSR_PRECISERR_Pos (9U)
8956-
#define SCB_CFSR_PRECISERR_Msk (0x1U << SCB_CFSR_PRECISERR_Pos) /*!< 0x00000200 */
89578943
#define SCB_CFSR_PRECISERR SCB_CFSR_PRECISERR_Msk /*!< Precise data bus error */
8958-
#define SCB_CFSR_IMPRECISERR_Pos (10U)
8959-
#define SCB_CFSR_IMPRECISERR_Msk (0x1U << SCB_CFSR_IMPRECISERR_Pos) /*!< 0x00000400 */
89608944
#define SCB_CFSR_IMPRECISERR SCB_CFSR_IMPRECISERR_Msk /*!< Imprecise data bus error */
8961-
#define SCB_CFSR_UNSTKERR_Pos (11U)
8962-
#define SCB_CFSR_UNSTKERR_Msk (0x1U << SCB_CFSR_UNSTKERR_Pos) /*!< 0x00000800 */
89638945
#define SCB_CFSR_UNSTKERR SCB_CFSR_UNSTKERR_Msk /*!< Unstacking error */
8964-
#define SCB_CFSR_STKERR_Pos (12U)
8965-
#define SCB_CFSR_STKERR_Msk (0x1U << SCB_CFSR_STKERR_Pos) /*!< 0x00001000 */
89668946
#define SCB_CFSR_STKERR SCB_CFSR_STKERR_Msk /*!< Stacking error */
8967-
#define SCB_CFSR_BFARVALID_Pos (15U)
8968-
#define SCB_CFSR_BFARVALID_Msk (0x1U << SCB_CFSR_BFARVALID_Pos) /*!< 0x00008000 */
89698947
#define SCB_CFSR_BFARVALID SCB_CFSR_BFARVALID_Msk /*!< Bus Fault Address Register address valid flag */
89708948
/*!< UFSR */
8971-
#define SCB_CFSR_UNDEFINSTR_Pos (16U)
8972-
#define SCB_CFSR_UNDEFINSTR_Msk (0x1U << SCB_CFSR_UNDEFINSTR_Pos) /*!< 0x00010000 */
89738949
#define SCB_CFSR_UNDEFINSTR SCB_CFSR_UNDEFINSTR_Msk /*!< The processor attempt to excecute an undefined instruction */
8974-
#define SCB_CFSR_INVSTATE_Pos (17U)
8975-
#define SCB_CFSR_INVSTATE_Msk (0x1U << SCB_CFSR_INVSTATE_Pos) /*!< 0x00020000 */
89768950
#define SCB_CFSR_INVSTATE SCB_CFSR_INVSTATE_Msk /*!< Invalid combination of EPSR and instruction */
8977-
#define SCB_CFSR_INVPC_Pos (18U)
8978-
#define SCB_CFSR_INVPC_Msk (0x1U << SCB_CFSR_INVPC_Pos) /*!< 0x00040000 */
89798951
#define SCB_CFSR_INVPC SCB_CFSR_INVPC_Msk /*!< Attempt to load EXC_RETURN into pc illegally */
8980-
#define SCB_CFSR_NOCP_Pos (19U)
8981-
#define SCB_CFSR_NOCP_Msk (0x1U << SCB_CFSR_NOCP_Pos) /*!< 0x00080000 */
89828952
#define SCB_CFSR_NOCP SCB_CFSR_NOCP_Msk /*!< Attempt to use a coprocessor instruction */
8983-
#define SCB_CFSR_UNALIGNED_Pos (24U)
8984-
#define SCB_CFSR_UNALIGNED_Msk (0x1U << SCB_CFSR_UNALIGNED_Pos) /*!< 0x01000000 */
89858953
#define SCB_CFSR_UNALIGNED SCB_CFSR_UNALIGNED_Msk /*!< Fault occurs when there is an attempt to make an unaligned memory access */
8986-
#define SCB_CFSR_DIVBYZERO_Pos (25U)
8987-
#define SCB_CFSR_DIVBYZERO_Msk (0x1U << SCB_CFSR_DIVBYZERO_Pos) /*!< 0x02000000 */
89888954
#define SCB_CFSR_DIVBYZERO SCB_CFSR_DIVBYZERO_Msk /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */
89898955

89908956
/******************* Bit definition for SCB_HFSR register *******************/

‎targets/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/device/stm32l151xc.h

Lines changed: 0 additions & 34 deletions
Original file line numberDiff line numberDiff line change
@@ -8481,58 +8481,24 @@ typedef struct
84818481

84828482
/******************* Bit definition for SCB_CFSR register *******************/
84838483
/*!< MFSR */
8484-
#define SCB_CFSR_IACCVIOL_Pos (0U)
8485-
#define SCB_CFSR_IACCVIOL_Msk (0x1U << SCB_CFSR_IACCVIOL_Pos) /*!< 0x00000001 */
84868484
#define SCB_CFSR_IACCVIOL SCB_CFSR_IACCVIOL_Msk /*!< Instruction access violation */
8487-
#define SCB_CFSR_DACCVIOL_Pos (1U)
8488-
#define SCB_CFSR_DACCVIOL_Msk (0x1U << SCB_CFSR_DACCVIOL_Pos) /*!< 0x00000002 */
84898485
#define SCB_CFSR_DACCVIOL SCB_CFSR_DACCVIOL_Msk /*!< Data access violation */
8490-
#define SCB_CFSR_MUNSTKERR_Pos (3U)
8491-
#define SCB_CFSR_MUNSTKERR_Msk (0x1U << SCB_CFSR_MUNSTKERR_Pos) /*!< 0x00000008 */
84928486
#define SCB_CFSR_MUNSTKERR SCB_CFSR_MUNSTKERR_Msk /*!< Unstacking error */
8493-
#define SCB_CFSR_MSTKERR_Pos (4U)
8494-
#define SCB_CFSR_MSTKERR_Msk (0x1U << SCB_CFSR_MSTKERR_Pos) /*!< 0x00000010 */
84958487
#define SCB_CFSR_MSTKERR SCB_CFSR_MSTKERR_Msk /*!< Stacking error */
8496-
#define SCB_CFSR_MMARVALID_Pos (7U)
8497-
#define SCB_CFSR_MMARVALID_Msk (0x1U << SCB_CFSR_MMARVALID_Pos) /*!< 0x00000080 */
84988488
#define SCB_CFSR_MMARVALID SCB_CFSR_MMARVALID_Msk /*!< Memory Manage Address Register address valid flag */
84998489
/*!< BFSR */
8500-
#define SCB_CFSR_IBUSERR_Pos (8U)
8501-
#define SCB_CFSR_IBUSERR_Msk (0x1U << SCB_CFSR_IBUSERR_Pos) /*!< 0x00000100 */
85028490
#define SCB_CFSR_IBUSERR SCB_CFSR_IBUSERR_Msk /*!< Instruction bus error flag */
8503-
#define SCB_CFSR_PRECISERR_Pos (9U)
8504-
#define SCB_CFSR_PRECISERR_Msk (0x1U << SCB_CFSR_PRECISERR_Pos) /*!< 0x00000200 */
85058491
#define SCB_CFSR_PRECISERR SCB_CFSR_PRECISERR_Msk /*!< Precise data bus error */
8506-
#define SCB_CFSR_IMPRECISERR_Pos (10U)
8507-
#define SCB_CFSR_IMPRECISERR_Msk (0x1U << SCB_CFSR_IMPRECISERR_Pos) /*!< 0x00000400 */
85088492
#define SCB_CFSR_IMPRECISERR SCB_CFSR_IMPRECISERR_Msk /*!< Imprecise data bus error */
8509-
#define SCB_CFSR_UNSTKERR_Pos (11U)
8510-
#define SCB_CFSR_UNSTKERR_Msk (0x1U << SCB_CFSR_UNSTKERR_Pos) /*!< 0x00000800 */
85118493
#define SCB_CFSR_UNSTKERR SCB_CFSR_UNSTKERR_Msk /*!< Unstacking error */
8512-
#define SCB_CFSR_STKERR_Pos (12U)
8513-
#define SCB_CFSR_STKERR_Msk (0x1U << SCB_CFSR_STKERR_Pos) /*!< 0x00001000 */
85148494
#define SCB_CFSR_STKERR SCB_CFSR_STKERR_Msk /*!< Stacking error */
8515-
#define SCB_CFSR_BFARVALID_Pos (15U)
8516-
#define SCB_CFSR_BFARVALID_Msk (0x1U << SCB_CFSR_BFARVALID_Pos) /*!< 0x00008000 */
85178495
#define SCB_CFSR_BFARVALID SCB_CFSR_BFARVALID_Msk /*!< Bus Fault Address Register address valid flag */
85188496
/*!< UFSR */
8519-
#define SCB_CFSR_UNDEFINSTR_Pos (16U)
8520-
#define SCB_CFSR_UNDEFINSTR_Msk (0x1U << SCB_CFSR_UNDEFINSTR_Pos) /*!< 0x00010000 */
85218497
#define SCB_CFSR_UNDEFINSTR SCB_CFSR_UNDEFINSTR_Msk /*!< The processor attempt to excecute an undefined instruction */
8522-
#define SCB_CFSR_INVSTATE_Pos (17U)
8523-
#define SCB_CFSR_INVSTATE_Msk (0x1U << SCB_CFSR_INVSTATE_Pos) /*!< 0x00020000 */
85248498
#define SCB_CFSR_INVSTATE SCB_CFSR_INVSTATE_Msk /*!< Invalid combination of EPSR and instruction */
8525-
#define SCB_CFSR_INVPC_Pos (18U)
8526-
#define SCB_CFSR_INVPC_Msk (0x1U << SCB_CFSR_INVPC_Pos) /*!< 0x00040000 */
85278499
#define SCB_CFSR_INVPC SCB_CFSR_INVPC_Msk /*!< Attempt to load EXC_RETURN into pc illegally */
8528-
#define SCB_CFSR_NOCP_Pos (19U)
8529-
#define SCB_CFSR_NOCP_Msk (0x1U << SCB_CFSR_NOCP_Pos) /*!< 0x00080000 */
85308500
#define SCB_CFSR_NOCP SCB_CFSR_NOCP_Msk /*!< Attempt to use a coprocessor instruction */
8531-
#define SCB_CFSR_UNALIGNED_Pos (24U)
8532-
#define SCB_CFSR_UNALIGNED_Msk (0x1U << SCB_CFSR_UNALIGNED_Pos) /*!< 0x01000000 */
85338501
#define SCB_CFSR_UNALIGNED SCB_CFSR_UNALIGNED_Msk /*!< Fault occurs when there is an attempt to make an unaligned memory access */
8534-
#define SCB_CFSR_DIVBYZERO_Pos (25U)
8535-
#define SCB_CFSR_DIVBYZERO_Msk (0x1U << SCB_CFSR_DIVBYZERO_Pos) /*!< 0x02000000 */
85368502
#define SCB_CFSR_DIVBYZERO SCB_CFSR_DIVBYZERO_Msk /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */
85378503

85388504
/******************* Bit definition for SCB_HFSR register *******************/

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