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Merge pull request #1812 from bcostm/fix_f091rc_hsi_clock
[NUCLEO_F091RC] Fix HSI clock configuration issue.
2 parents c40581c + aef000d commit 486d7e8

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hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/system_stm32f0xx.c

Lines changed: 9 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -363,14 +363,14 @@ void SetSysClock(void)
363363
{
364364
while(1)
365365
{
366-
// [TODO] Put something here to tell the user that a problem occured...
366+
// HSI did not start !!!
367367
}
368368
}
369369
}
370370
}
371371

372-
// Output clock on MCO pin(PA8) for debugging purpose
373-
//HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_SYSCLK, RCC_MCO_NODIV); // 48 MHz
372+
// Output system clock on MCO pin(PA8) for debugging purpose
373+
//HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_SYSCLK, RCC_MCO_DIV8); // 48MHz/8=6MHz
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}
375375

376376
#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
@@ -389,7 +389,6 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
389389
return 0; // FAIL
390390
}
391391

392-
393392
// Select HSE oscillator as PLL source
394393
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
395394
if (bypass == 0) {
@@ -414,11 +413,11 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
414413
return 0; // FAIL
415414
}
416415

417-
// Output clock on MCO pin(PA8) for debugging purpose
416+
// Output HSE clock on MCO pin(PA8) for debugging purpose
418417
//if (bypass == 0)
419-
// HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSE, RCC_MCO_DIV2); // 4 MHz with xtal
418+
// HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSE, RCC_MCO_DIV2); // 8MHz/2=4MHz with xtal
420419
//else
421-
// HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSE, RCC_MCO_DIV4); // 2 MHz with ST-Link MCO
420+
// HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSE, RCC_MCO_DIV4); // 8MHz/4=2MHz with ST-Link MCO
422421

423422
return 1; // OK
424423
}
@@ -444,7 +443,7 @@ uint8_t SetSysClock_PLL_HSI(void)
444443
RCC_OscInitStruct.LSIState = RCC_LSI_OFF;
445444
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
446445
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; // HSI div 2
447-
RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV1;
446+
RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV2;
448447
RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL12;
449448
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
450449
return 0; // FAIL
@@ -459,8 +458,8 @@ uint8_t SetSysClock_PLL_HSI(void)
459458
return 0; // FAIL
460459
}
461460

462-
// Output clock on MCO1 pin(PA8) for debugging purpose
463-
//HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSI, RCC_MCO_DIV1); // 48 MHz
461+
// Output HSI clock on MCO1 pin(PA8) for debugging purpose
462+
//HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSI, RCC_MCO_DIV2); // 8MHz/2=4MHz
464463

465464
return 1; // OK
466465
}

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