Skip to content

Commit 489e52e

Browse files
0xc01700xc0170
authored
Merge pull request #9410 from jeromecoutant/PR_F756_L486
STM32F756 and STM32L486 alignment with STM32F746 and STM32L476
2 parents e3cf2e4 + 7876a65 commit 489e52e

File tree

16 files changed

+145
-39
lines changed

16 files changed

+145
-39
lines changed

‎targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/device/TOOLCHAIN_ARM_STD/stm32f746xg.sct

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -51,15 +51,15 @@
5151
#define MBED_RAM0_START (MBED_CRASH_REPORT_RAM_START + MBED_CRASH_REPORT_RAM_SIZE)
5252
#define MBED_RAM0_SIZE (MBED_RAM_SIZE - MBED_VECTTABLE_RAM_SIZE - MBED_CRASH_REPORT_RAM_SIZE)
5353

54-
; STM32F746NG: 1024 KB FLASH (0x100000) + 320 KB SRAM (0x50000)
54+
; STM32F746xG: 1024 KB FLASH (0x100000) + 320 KB SRAM (0x50000)
5555
LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
5656

5757
ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address
5858
*.o (RESET, +First)
5959
*(InRoot$$Sections)
6060
.ANY (+RO)
6161
}
62-
62+
6363
RW_m_crash_data MBED_CRASH_REPORT_RAM_START EMPTY MBED_CRASH_REPORT_RAM_SIZE { ; RW data
6464
}
6565

‎targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/device/TOOLCHAIN_GCC_ARM/STM32F746xG.ld

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -93,7 +93,7 @@ SECTIONS
9393

9494
__etext = .;
9595
_sidata = .;
96-
96+
9797
.crash_data_ram :
9898
{
9999
. = ALIGN(8);
@@ -104,7 +104,7 @@ SECTIONS
104104
. += M_CRASH_DATA_RAM_SIZE;
105105
. = ALIGN(8);
106106
__CRASH_DATA_RAM_END__ = .; /* Define a global symbol at data end */
107-
} > RAM
107+
} > RAM
108108

109109
.data : AT (__etext)
110110
{

‎targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/device/TOOLCHAIN_GCC_ARM/startup_stm32f746xx.S

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -235,12 +235,12 @@ g_pfnVectors:
235235
.word UART7_IRQHandler /* UART7 */
236236
.word UART8_IRQHandler /* UART8 */
237237
.word SPI4_IRQHandler /* SPI4 */
238-
.word SPI5_IRQHandler /* SPI5 */
239-
.word SPI6_IRQHandler /* SPI6 */
240-
.word SAI1_IRQHandler /* SAI1 */
241-
.word LTDC_IRQHandler /* LTDC */
242-
.word LTDC_ER_IRQHandler /* LTDC error */
243-
.word DMA2D_IRQHandler /* DMA2D */
238+
.word SPI5_IRQHandler /* SPI5 */
239+
.word SPI6_IRQHandler /* SPI6 */
240+
.word SAI1_IRQHandler /* SAI1 */
241+
.word LTDC_IRQHandler /* LTDC */
242+
.word LTDC_ER_IRQHandler /* LTDC error */
243+
.word DMA2D_IRQHandler /* DMA2D */
244244
.word SAI2_IRQHandler /* SAI2 */
245245
.word QUADSPI_IRQHandler /* QUADSPI */
246246
.word LPTIM1_IRQHandler /* LPTIM1 */
@@ -577,5 +577,5 @@ g_pfnVectors:
577577
.weak SPDIF_RX_IRQHandler
578578
.thumb_set SPDIF_RX_IRQHandler,Default_Handler
579579

580-
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
580+
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
581581

‎targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/device/cmsis_nvic.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -34,7 +34,7 @@
3434
// CORE: 16 vectors = 64 bytes from 0x00 to 0x3F
3535
// MCU Peripherals: 98 vectors = 392 bytes from 0x40 to 0x1C7
3636
// Total: 114 vectors = 456 bytes (0x1C8) to be reserved in RAM
37-
#define NVIC_NUM_VECTORS 114
37+
#define NVIC_NUM_VECTORS 114
3838
#define NVIC_RAM_VECTOR_ADDRESS 0x20000000 // Vectors positioned at start of RAM
3939

4040
#endif

‎targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/TARGET_NUCLEO_F756ZG/system_clock.c

Lines changed: 5 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -30,6 +30,7 @@
3030
**/
3131

3232
#include "stm32f7xx.h"
33+
#include "nvic_addr.h"
3334
#include "mbed_error.h"
3435

3536
/*!< Uncomment the following line if you need to relocate your vector Table in
@@ -92,7 +93,7 @@ void SystemInit(void)
9293
#ifdef VECT_TAB_SRAM
9394
SCB->VTOR = RAMDTCM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
9495
#else
95-
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
96+
SCB->VTOR = NVIC_FLASH_VECTOR_ADDRESS; /* Vector Table Relocation in Internal FLASH */
9697
#endif
9798

9899
}
@@ -208,14 +209,14 @@ uint8_t SetSysClock_PLL_HSI(void)
208209
__PWR_CLK_ENABLE();
209210

210211
// Enable HSI oscillator and activate PLL with HSI as source
211-
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
212+
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
212213
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
213214
RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
214215
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
215216
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
216217
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
217-
RCC_OscInitStruct.PLL.PLLM = 8; // VCO input clock = 1 MHz (16 MHz / 16)
218-
RCC_OscInitStruct.PLL.PLLN = 216; // VCO output clock = 432 MHz (1 MHz * 432)
218+
RCC_OscInitStruct.PLL.PLLM = 8; // VCO input clock = 2 MHz (16 MHz / 8)
219+
RCC_OscInitStruct.PLL.PLLN = 216; // VCO output clock = 432 MHz (2 MHz * 216)
219220
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; // PLLCLK = 216 MHz (432 MHz / 2)
220221
RCC_OscInitStruct.PLL.PLLQ = 9;
221222

‎targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/device/TOOLCHAIN_ARM_STD/stm32f756xg.sct

Lines changed: 25 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -28,27 +28,47 @@
2828
; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
2929
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3030

31+
#if !defined(MBED_APP_START)
32+
#define MBED_APP_START 0x08000000
33+
#endif
34+
35+
#if !defined(MBED_APP_SIZE)
36+
#define MBED_APP_SIZE 0x100000
37+
#endif
38+
3139
#if !defined(MBED_BOOT_STACK_SIZE)
3240
#define MBED_BOOT_STACK_SIZE 0x400
3341
#endif
3442

3543
#define Stack_Size MBED_BOOT_STACK_SIZE
3644

37-
; STM32F756ZG: 1024 KB FLASH (0x100000) + 320 KB SRAM (0x50000)
38-
LR_IROM1 0x08000000 0x100000 { ; load region size_region
45+
#define MBED_RAM_START 0x20000000
46+
#define MBED_RAM_SIZE 0x50000
47+
#define MBED_VECTTABLE_RAM_START (MBED_RAM_START)
48+
#define MBED_VECTTABLE_RAM_SIZE 0x1C8
49+
#define MBED_CRASH_REPORT_RAM_START (MBED_VECTTABLE_RAM_START + MBED_VECTTABLE_RAM_SIZE)
50+
#define MBED_CRASH_REPORT_RAM_SIZE 0x100
51+
#define MBED_RAM0_START (MBED_CRASH_REPORT_RAM_START + MBED_CRASH_REPORT_RAM_SIZE)
52+
#define MBED_RAM0_SIZE (MBED_RAM_SIZE - MBED_VECTTABLE_RAM_SIZE - MBED_CRASH_REPORT_RAM_SIZE)
3953

40-
ER_IROM1 0x08000000 0x100000 { ; load address = execution address
54+
; STM32F746xG: 1024 KB FLASH (0x100000) + 320 KB SRAM (0x50000)
55+
LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
56+
57+
ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address
4158
*.o (RESET, +First)
4259
*(InRoot$$Sections)
4360
.ANY (+RO)
4461
}
4562

63+
RW_m_crash_data MBED_CRASH_REPORT_RAM_START EMPTY MBED_CRASH_REPORT_RAM_SIZE { ; RW data
64+
}
65+
4666
; Total: 114 vectors = 456 bytes (0x1C8) to be reserved in RAM
47-
RW_IRAM1 (0x20000000+0x1C8) (0x50000-0x1C8-Stack_Size) { ; RW data
67+
RW_IRAM1 (MBED_RAM0_START) (MBED_RAM0_SIZE-Stack_Size) { ; RW data
4868
.ANY (+RW +ZI)
4969
}
5070

51-
ARM_LIB_STACK (0x20000000+0x50000) EMPTY -Stack_Size { ; stack
71+
ARM_LIB_STACK (MBED_RAM0_START+MBED_RAM0_SIZE) EMPTY -Stack_Size { ; stack
5272
}
5373
}
5474

‎targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/device/TOOLCHAIN_GCC_ARM/STM32F756xG.ld

Lines changed: 23 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -6,9 +6,19 @@
66

77
STACK_SIZE = MBED_BOOT_STACK_SIZE;
88

9+
#if !defined(MBED_APP_START)
10+
#define MBED_APP_START 0x08000000
11+
#endif
12+
13+
#if !defined(MBED_APP_SIZE)
14+
#define MBED_APP_SIZE 1024K
15+
#endif
16+
17+
M_CRASH_DATA_RAM_SIZE = 0x100;
18+
919
MEMORY
1020
{
11-
FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 1024K
21+
FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE
1222
RAM (rwx) : ORIGIN = 0x200001C8, LENGTH = 320K - 0x1C8
1323
}
1424

@@ -84,6 +94,18 @@ SECTIONS
8494
__etext = .;
8595
_sidata = .;
8696

97+
.crash_data_ram :
98+
{
99+
. = ALIGN(8);
100+
__CRASH_DATA_RAM__ = .;
101+
__CRASH_DATA_RAM_START__ = .; /* Create a global symbol at data start */
102+
KEEP(*(.keep.crash_data_ram))
103+
*(.m_crash_data_ram) /* This is a user defined section */
104+
. += M_CRASH_DATA_RAM_SIZE;
105+
. = ALIGN(8);
106+
__CRASH_DATA_RAM_END__ = .; /* Define a global symbol at data end */
107+
} > RAM
108+
87109
.data : AT (__etext)
88110
{
89111
__data_start__ = .;

‎targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/device/TOOLCHAIN_IAR/stm32f756xg.icf

Lines changed: 15 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1,12 +1,17 @@
1+
if (!isdefinedsymbol(MBED_APP_START)) { define symbol MBED_APP_START = 0x08000000; }
2+
if (!isdefinedsymbol(MBED_APP_SIZE)) { define symbol MBED_APP_SIZE = 0x100000; }
3+
14
/* [ROM = 1024kb = 0x100000] */
2-
define symbol __intvec_start__ = 0x08000000;
3-
define symbol __region_ROM_start__ = 0x08000000;
4-
define symbol __region_ROM_end__ = 0x080FFFFF;
5+
define symbol __intvec_start__ = MBED_APP_START;
6+
define symbol __region_ROM_start__ = MBED_APP_START;
7+
define symbol __region_ROM_end__ = MBED_APP_START + MBED_APP_SIZE - 1;
58

69
/* [RAM = 320kb = 0x50000] Vector table dynamic copy: 114 vectors = 456 bytes (0x1C8) to be reserved in RAM */
710
define symbol __NVIC_start__ = 0x20000000;
811
define symbol __NVIC_end__ = 0x200001C7; /* Aligned on 8 bytes */
9-
define symbol __region_RAM_start__ = 0x200001C8;
12+
define symbol __region_CRASH_DATA_RAM_start__ = 0x200001C8;
13+
define symbol __region_CRASH_DATA_RAM_end__ = 0x200002C7;
14+
define symbol __region_RAM_start__ = 0x200002C8;
1015
define symbol __region_RAM_end__ = 0x2004FFFF;
1116

1217
define symbol __region_ITCMRAM_start__ = 0x00000000;
@@ -16,14 +21,19 @@ define symbol __region_ITCMRAM_end__ = 0x00003FFF;
1621
define memory mem with size = 4G;
1722
define region ROM_region = mem:[from __region_ROM_start__ to __region_ROM_end__];
1823
define region RAM_region = mem:[from __region_RAM_start__ to __region_RAM_end__];
24+
define region CRASH_DATA_RAM_region = mem:[from __region_CRASH_DATA_RAM_start__ to __region_CRASH_DATA_RAM_end__];
1925
define region ITCMRAM_region = mem:[from __region_ITCMRAM_start__ to __region_ITCMRAM_end__];
2026

27+
/* Define Crash Data Symbols */
28+
define exported symbol __CRASH_DATA_RAM_START__ = __region_CRASH_DATA_RAM_start__;
29+
define exported symbol __CRASH_DATA_RAM_END__ = __region_CRASH_DATA_RAM_end__;
30+
2131
/* Stack and Heap */
2232
if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) {
2333
define symbol MBED_BOOT_STACK_SIZE = 0x400;
2434
}
2535
define symbol __size_cstack__ = MBED_BOOT_STACK_SIZE;
26-
define symbol __size_heap__ = 0x10000;
36+
define symbol __size_heap__ = 0x13000;
2737
define block CSTACK with alignment = 8, size = __size_cstack__ { };
2838
define block HEAP with alignment = 8, size = __size_heap__ { };
2939
define block STACKHEAP with fixed order { block HEAP, block CSTACK };

‎targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/objects.h

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -58,6 +58,16 @@ struct trng_s {
5858
RNG_HandleTypeDef handle;
5959
};
6060

61+
struct qspi_s {
62+
QSPI_HandleTypeDef handle;
63+
PinName io0;
64+
PinName io1;
65+
PinName io2;
66+
PinName io3;
67+
PinName sclk;
68+
PinName ssel;
69+
};
70+
6171
#include "common_objects.h"
6272

6373
#ifdef __cplusplus

‎targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/device/TOOLCHAIN_ARM_STD/stm32l476xx.sct

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -60,11 +60,11 @@ LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
6060

6161
RW_m_crash_data MBED_CRASH_REPORT_RAM_START EMPTY MBED_CRASH_REPORT_RAM_SIZE { ; RW data
6262
}
63-
63+
6464
RW_IRAM1 MBED_RAM0_START MBED_RAM0_SIZE-Stack_Size { ; RW data 96k L4-SRAM1
6565
.ANY (+RW +ZI)
6666
}
67-
67+
6868
; Total: 98 vectors = 392 bytes (0x188) to be reserved in RAM
6969
RW_IRAM2 (0x10000000+0x188) (0x08000-0x188) { ; RW data 32k L4-ECC-SRAM2 retained in standby
7070
.ANY (+RW +ZI)

‎targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/device/TOOLCHAIN_GCC_ARM/STM32L476XX.ld

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -16,7 +16,7 @@ STACK_SIZE = MBED_BOOT_STACK_SIZE;
1616

1717
/* Linker script to configure memory regions. */
1818
MEMORY
19-
{
19+
{
2020
FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE
2121
SRAM2 (rwx) : ORIGIN = 0x10000188, LENGTH = 32k - 0x188
2222
SRAM1 (rwx) : ORIGIN = 0x20000000, LENGTH = 96k
@@ -26,7 +26,7 @@ MEMORY
2626
* with other linker script that defines memory regions FLASH and RAM.
2727
* It references following symbols, which must be defined in code:
2828
* Reset_Handler : Entry of reset handler
29-
*
29+
*
3030
* It defines following symbols, which code can use without definition:
3131
* __exidx_start
3232
* __exidx_end
@@ -93,7 +93,7 @@ SECTIONS
9393

9494
__etext = .;
9595
_sidata = .;
96-
96+
9797
.crash_data_ram :
9898
{
9999
. = ALIGN(8);
@@ -104,7 +104,7 @@ SECTIONS
104104
. += M_CRASH_DATA_RAM_SIZE;
105105
. = ALIGN(8);
106106
__CRASH_DATA_RAM_END__ = .; /* Define a global symbol at data end */
107-
} > SRAM1
107+
} > SRAM1
108108

109109
.data : AT (__etext)
110110
{

‎targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/TARGET_NUCLEO_L486RG/system_clock.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -97,7 +97,7 @@ void SystemInit(void)
9797
#ifdef VECT_TAB_SRAM
9898
SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
9999
#else
100-
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
100+
SCB->VTOR = NVIC_FLASH_VECTOR_ADDRESS; /* Vector Table Relocation in Internal FLASH */
101101
#endif
102102

103103
}

‎targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/device/TOOLCHAIN_ARM_STD/stm32l486xx.sct

Lines changed: 14 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -36,6 +36,13 @@
3636
#define MBED_APP_SIZE 0x100000
3737
#endif
3838

39+
#define MBED_RAM_START 0x20000000
40+
#define MBED_RAM_SIZE 0x00018000
41+
#define MBED_CRASH_REPORT_RAM_START (MBED_RAM_START)
42+
#define MBED_CRASH_REPORT_RAM_SIZE 0x100
43+
#define MBED_RAM0_START (MBED_CRASH_REPORT_RAM_START + MBED_CRASH_REPORT_RAM_SIZE)
44+
#define MBED_RAM0_SIZE (MBED_RAM_SIZE - MBED_CRASH_REPORT_RAM_SIZE)
45+
3946
#if !defined(MBED_BOOT_STACK_SIZE)
4047
#define MBED_BOOT_STACK_SIZE 0x400
4148
#endif
@@ -51,15 +58,20 @@ LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
5158
.ANY (+RO)
5259
}
5360

54-
RW_IRAM1 0x20000000 0x00018000-Stack_Size { ; RW data 96k L4-SRAM1
61+
RW_m_crash_data MBED_CRASH_REPORT_RAM_START EMPTY MBED_CRASH_REPORT_RAM_SIZE { ; RW data
62+
}
63+
64+
RW_IRAM1 MBED_RAM0_START MBED_RAM0_SIZE-Stack_Size { ; RW data 96k L4-SRAM1
5565
.ANY (+RW +ZI)
5666
}
67+
5768
; Total: 98 vectors = 392 bytes (0x188) to be reserved in RAM
5869
RW_IRAM2 (0x10000000+0x188) (0x08000-0x188) { ; RW data 32k L4-ECC-SRAM2 retained in standby
5970
.ANY (+RW +ZI)
6071
}
6172

62-
ARM_LIB_STACK (0x20000000+0x00018000) EMPTY -Stack_Size { ; stack
73+
ARM_LIB_STACK (MBED_RAM0_START+MBED_RAM0_SIZE) EMPTY -Stack_Size { ; stack
6374
}
75+
6476
}
6577

‎targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/device/TOOLCHAIN_GCC_ARM/STM32L486XX.ld

Lines changed: 15 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -6,6 +6,8 @@
66
#define MBED_APP_SIZE 1024k
77
#endif
88

9+
M_CRASH_DATA_RAM_SIZE = 0x100;
10+
911
#if !defined(MBED_BOOT_STACK_SIZE)
1012
#define MBED_BOOT_STACK_SIZE 0x400
1113
#endif
@@ -15,7 +17,7 @@ STACK_SIZE = MBED_BOOT_STACK_SIZE;
1517
/* Linker script to configure memory regions. */
1618
MEMORY
1719
{
18-
FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE
20+
FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE
1921
SRAM2 (rwx) : ORIGIN = 0x10000188, LENGTH = 32k - 0x188
2022
SRAM1 (rwx) : ORIGIN = 0x20000000, LENGTH = 96k
2123
}
@@ -92,6 +94,18 @@ SECTIONS
9294
__etext = .;
9395
_sidata = .;
9496

97+
.crash_data_ram :
98+
{
99+
. = ALIGN(8);
100+
__CRASH_DATA_RAM__ = .;
101+
__CRASH_DATA_RAM_START__ = .; /* Create a global symbol at data start */
102+
KEEP(*(.keep.crash_data_ram))
103+
*(.m_crash_data_ram) /* This is a user defined section */
104+
. += M_CRASH_DATA_RAM_SIZE;
105+
. = ALIGN(8);
106+
__CRASH_DATA_RAM_END__ = .; /* Define a global symbol at data end */
107+
} > SRAM1
108+
95109
.data : AT (__etext)
96110
{
97111
__data_start__ = .;

0 commit comments

Comments
 (0)